Small Stack Based Computer Compiler with a 9-bit Opcode, 8-bit Data Core

Small Stack Based Computer Compiler with a 9-bit Opcode, 8-bit Data Core


Category: Processor

Created: January 02, 2014

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: Others



SSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode, 8-bit data core. It creates vendor-independent, high-speed, low fabric utilization micro controllers for FPGAs. It has been used in Spartan-3A, Spartan-6, Virtex-6, and Artix-7 FPGAs and has been built for Altera, Lattice, and other Xilinx devices. It is faster and usually smaller than vendor provided processors.

The compiler takes an architecture file that describes the micro controller memory spaces, inputs and outputs, and peripherals and which specifies the HDL language and source assembly. It generates a single HDL module implementing the entire micro controller. No user-written HDL is required to instantiate I/Os, program memory, etc.

SSBCC has been used for the following projects:

operate a media translator from a parallel camera interface to an OMAP GPMC interface, detect and report bus errors and hardware errors, and act as an SPI slave to the OMAP

operate two UART interfaces and multiple PWM controlled 2-lead bi-color LEDs

operate and monitor the Artix-7 fabric in a Zynq system using AXI4-Lite master and slave buses, I2C buses for timing-critical voltage measurements


The computer compiler, the assembler, and several peripherals have been been working since early 2012.

The only external tool required is Python 2.7.


Snapshots of the project can be downloaded from opencores. The code is maintained at

Questions can be e-mailed to