Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)

Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)


Category: Processor

Created: January 05, 2010

Updated: January 27, 2020

Language: Verilog & VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: BSD


This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or slave cores as an 8-bit master device. There is no native hardware handshake mechanism at PicoBlaze (TM) ports, so wishbone wait-state recognition is done by software polling. Some standard wishbone slave peripherals like GPIO and UART are included as well.


  • Multi HDL language implementation VHDL and Verilog (R)
  • Assembler subroutines
  • Simulation testbench and command file
  • Notepad++ custom syntax highlighter for assembler
  • Synthesizable GPIO example
  • Synthesizable UART example, using Xilinx (R) UART macros together with a wishbone slave wrapper
  • Baud rate calculation script
  • Implementation files for low cost AVNET (R) Spartan(R)-3A Evaluation Kit using Xilinx ISE (R) 13.1

Getting Started

  1. Prerequisites: Xilinx ISE (R) and ModelSim Xilinx Edition III (R)
  2. Download wb4pb sources and be sure to keep directory structure!
  3. Download PicoBlaze (TM) from Xilinx (R) (registration required)
  4. Copy kcpsm3.v and kcpsm3.vhd to rtl directory
  5. Open in a text editor and customize "set wd ..." and "set isVHDL ..." lines
  6. Start ModelSim (R) and execute DO-File (Menu->Tools->TCL->Execute Macro...)

Synthesis Results

xc3s400a-4ft256 device using Xilinx ISE (R) 13.1 with default settings

GPIO example VHDLGPIO example Verilog (R)UART example VHDLUART example Verilog (R)
max. frequency97.220MHz102.082MHz101.647MHz100.553MHz
clock nets1111
slice utilization3%3%5%5%