SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

SardMIPS - Synthesizable Parametric IP Core of 32-bit RISC Processor

Details

Category: System on Chip

Created: January 21, 2006

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: GPL

Description

Embedded MIPS R2000

It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable.

Features

- feature1
- feature1.1
-feature1.2
-feature2

Status

Some bugs was fix.

-> correct bug when intterupt occur during MFLO and MFHI instruction.

Now I'm working on the CP0

status 2