RISC microprocessor (DLX) in systemC Implementation

RISC microprocessor (DLX) in systemC Implementation


Category: Uncategorized

Created: May 19, 2006

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a


This is the basic datapath of DLX microprocessor that suports
Simple memory access instructions (lw, sw)
Arithmetic and logical instructions (add, sub, and, or, xor, addi, subi, ori, andi, xori)
Transport control inxtructions (beqz, bnez, j, jr)
Implementing these instructions, is the basis for the implemetation of the complete DLX instruction set architecture.
Additional information about the instruction set and capabilities can be found at: http://www.kroening.com/diplom/diplommain010.html
The implemetation is based on SystemC language, using the standar C++ tools like Visual studio 6.0 and GTK wave 1.3.19 (waveform simulator). The restrictions that systemCrafter has, are are taken into consideration in systemC implemetation.
SystemC description is then compiled to RTL VHDL using SystemCrafter (see www.systemcrafter.com) for further synthesis by downstream tools. For Xilinx FPGAs this is Xilinx XST and place and route tools.
When synthesize and verify the netlist of the circuit, the design is implemented into MEMECs Spartan-3 LC development kit.


Empty block

FILE: systemC_Implementation.rar

FILE: systemC_Implementation.rar
DESCRIPTION: SystemC description of datapath. The restrictions coming from systemCrafter are taking place. The block of memories (imem, rs_imem, rt_imem, regfile, mem_data) used inthe design, are black boxes at this stage, because memories are not synthesizable. In order to compile the systemC implemenatation, open the datapath.scproj and run gateLevel simulation. This will translate the systemC description into RTL VHDL.

FILE: datapath.pdf

FILE: datapath.pdf
DESCRIPTION: Scematic diagram of microcontroller's datapath

FILE: RegFile_SystemC_implementation.rar

FILE: RegFile_SystemC_implementation.rar
DESCRIPTION: This is the register file systemC description. Register file is implemeted by two dual port RAMS. The produced regfile.vhd will replace the one produced in systemC Implementation folder.

FILE: Xilinx_project_from_files_from_SystemC_implementation.rar

FILE: Xilinx_project_from_files_from_SystemC_implementation.rar
DESCRIPTION: This folder has the translated VHD project, when Xilinx ISE 7.1i is used for further synthesis of the design.

In order to create the project do the following:
Include to the project the file craft_gatelibrary.vhd. This file is on systemCrafter setup folder.
Replace all the block memories (mem_data, imem, rs_imem, rt_imem, dual_port_ram) with block memories greaded by Xilinx core generator.
After palce and route operation you can verify the netlist of the micorcontroller

The project can now be downloaded to any Xilinx FPGA


FILE: memories_core_jenerator_implementations.rar

FILE: memories_core_jenerator_implementations.rar
DESCRIPTION: This folder includes all the block of memories, needed during the implemetation, produced by ISE core generator.
In order to use these memories, copy and paste all the files into projects directory.
include to project only the .coe files

FILE: Readme-Instructions.doc

FILE: Readme-Instructions.doc