Simple Capture/Compare Timer with Multiple Capture/Compare Channels

Simple Capture/Compare Timer with Multiple Capture/Compare Channels

Details

Category: Uncategorized

Created: June 10, 2015

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: GPL

Description

SCCT is a Simple Capture/Compare Timer written in Verilog. It provides multiple capture/compare channels that use a common counter. Events occurring in the single channels thus can be related to a global time base. SCCT is developed as an IP core that can be attached to the Altera Avalon bus.