RTF Bitmap Multiple Display Controllers

RTF Bitmap Multiple Display Controllers


Category: Video Controller

Created: September 19, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

Additional info: FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


Video frame buffer. This core is a low to medium resolution bitmap display controller. It was engineered for use on the
Nexsys2 board, a Spartan3e FPGA board, but is readily adaptable to other environments. The core has
been upgraded for use on the Atlys FPGA board. The latest incarnation of the core is being developed on a Nexys4 board.

FT BMC Features

The FT version of the bitmap controller represents a further evolution of the bitmapped controller. The controller now supports the concept of graphics planes. The graphics plane of a pixel is output along with color information to allow multiple display controllers (eg sprite controller) to select which display controller has output priority.

The controller supports hardware accelerated pixel plot and fetch capability.

The controller accesses memory in 128 bit strips into which pixels are packed. 128 bits at a time are read in a single memory access. The memory access period is programmable.


- small size
- supports high, mid and low resolution bitmap display
- programmable display format (divide by 1,2, or 4).
- programmable color depth (8,16, or 32 bpp).
- 32 byte burst fetching
- memory bandwidth consideration
- video fifo
- independent video and bus clocks

- controller2
--- supports the concept of color planes and can indicate if colors should appear as backdrop or frontdrop
--- uses non-burst, 128 bit wide memory access

- controller3
--- supports more color depths: (6,8,9,12,15,16,24, and 32 bpp)
--- offers more display dividers (1 to 7 times)
--- uses non-burst, 128 bit wide memory access

- controller4
--- supports fewer color depths: (8,12,16,24, and 32 bpp)
--- incorporates a pixel plotting and fetching accelerator
--- is a larger core

- controller5
--- supports color depths: (8,12,16,20, and 32 bpp)
--- incorporates a pixel plotting and fetching accelerator
--- has a raster compare register for scan-line interrupts --- configurable bus master width of 128/64 or 32 bit accesses --- non-burst mode access

While small, this controller core has a number of interesting features. It features low resolution
(low resolution these days) bitmap display. The video clock and scanline may be divided by up to 4 to provide lower resolution displays. For instance a 340 x 192 x 8bpp display can be created using a 1366x768 display mode. Memory usage is then
about 64Kb. The design of the controller takes into consideration the amount of memory bandwidth available to
the system, using 32 byte burst fetches to fill a fifo.


The original controller fetches data in 32 byte bursts as the video fifo become empty. The 32 byte
burst fetches are geared towards allowing other devices in the system to access the same memory. So
that the peformance of the entire system isn't adverse. The controller relies on the memory system
to support burst mode fetchs.
The newer controllers don't use burst access, they simply use a wide memory port with normal access.

The controller uses three independent clocks, one each for bus timing and video timing.