There is a new sprite controller which operates differently from the original. The original used image caches and supported a color depth up to 32k colors. This additional new version does not use image caches and operates somewhat more simply. Instead it reads directly from memory. Sprite image data is loaded during the horizontal blanking interval. For the new version sprites are limited to three simultaneous colors plus transparent. However, pairs of sprites may be linked together to increase the simultaneous color selection to fifteen plus transparent. Sprite may be up to 32 pixels wide and 512 scan lines tall.
The new controller acts as a 64-bit slave device and as a 64-bit bus master. As a master the controller only performs bus read cycles. The controller is WISHBONE compatible.
This core provide hardware cursor / sprite capabilities. It supports alpha blending in the 32k color mode. The cursor characteristics are completely programmable. The core has been updated to reflect larger amounts of memory and resources available in newer devices.
- up to 32 sprites supported
- max size up to 32hx512v
- four colors simultaneously per sprite (3 + transparent)
- sprites linkable to increase color selection to 16
- 64-bit bus transfers
- parameterized number of sprites/cursors 1,2,4,6,8,14, or 32
- 4kB sprite image cache buffers
- each image cache is capable of holding multiple sprite images
- cache may be accessed like a memory by the processor
- an embedded DMA controller may also be used for sprite reload
- programmable image offset within cache
- programmable sprite width,height, and pixel size
- sprite width and height may vary from 1 to 256 pixels as long
as the product doesn't exceed 2048.
- pixels may be programmed to be 1 to 16 video clocks
both height and width are programmable
- programmable sprite position
- 8 or 16 bits for color
eg 32k color + 1 bit alpha blending indicator (1,5,5,5)
- fixed display and DMA priority sprite 0 highest, sprite 31 lowest
A new simpler core is currently under development
The core is currently being tested on an Atlys board and appears to be working.
The core is being tested with a Nexys4ddr board at present.