A “Shelf-life” for FinFETs? Samsung and TSMC Improve Node Density for RF
Single-digit node process is nothing new, but existing technology hampers RF performance due to parasitics. Samsung Foundry and TSMC seek to bring single-digit node performance to RF chips.
The quest for single-atom transistors seems a little closer in 2021, with major foundry releases by Samsung, TMSC, and IBM. Fabrication processes are continually in a state of advancement, with transistor sizes shrinking with each new generation, allowing for increased density and reduced power consumption in chips of a given physical space.
TSMC's timeline for node technology. Image used courtesy of TSMC
Why are these new foundry releases important to the development of modern electronics?
What are the high-level challenges that “non-RF” sub-10 nm wafers present when designing a chip for 5G?
These are a couple of questions that this article will attempt to address today as we cover these two announcements, which will start with Samsung.
Samsung Optimizes Wafers for RF Performance
According to Samsung, the reduction in node size is generally associated with a negative trade-off in parasitics, including increased resistance, loss of amplification performance, and power inefficiencies.
Although IBM unveiled the world’s first 2nm chip technology in May 2021, which is significantly smaller and more power-conscious, it does not appear to address Samsung’s concerns towards RF parasitics. These parasitics make other sub-10 nm wafers inappropriate for RF performance.
To address these issues, Samsung claims to have developed a unique architecture for the 8nm-scale called RFextremeFET (RFeFET), which claims to provide a 35% decrease in package size along with a comparable increase in power efficiencies.
Often neck-in-neck with other major foundries, like TSMC, Samsung continues to innovate on its existing node processes. However, as mentioned, TSMC is also innovating the node process when it comes to RF, with its N6RF.
TSMC’s N6RF Designed for 5G & Beyond
Based on TSMC’s 7nm fin field-effect transistor (FinFET) technology, the newly announced N6RF has been developed for the 5G market and the consumer WiFi 6/6e technology base, which also utilizes beamforming technology akin to 5G.
The physical construct of the 7nm finFET architecture. Image used courtesy of TSMC
Compared with TSMC’s previous generation RF-optimized wafer, the 16FFC, the new N6RF claims to have significantly improved power efficiency, a 3x increase in logic density, along with a corresponding reduction in transceiver size.
Performance metrics for the N6RF over the 16FFC. Image used courtesy of TSMC
Of course, as foundries improve node size, engineers will ask what is next after FinFET to drive performance gains?
Does FinFET Have a “Shelf-life”?
As the 5G market matures and radio applications multiply, the challenges for improving RF performance will not go away. Improving digital density and reducing power consumption will push the limits of FinFET architecture.
Although these new developments from Samsung and TSMC are focused on radio frequency performance, utilizing smaller node FinFET technology is necessary. However, it is essential to note that FinFET is likely not a future-proof solution to reducing power inefficiencies or boosting general-purpose processing power speed.
Gate-all-around (GAAFET) node technology, like the 2nm nanosheets from IBM, is projected to become the dominant process node technology over the next several years due to its claimed 75% lower power usage over 7nm technology.
The cost of fabrication often offsets performance improvement. Extreme ultraviolet lithography (the technology used to create TSMC's 7nm node) uses 13.5nm light to bake the wafers.
Currently, it is an expensive but maturing technology for use in the 5nm to 7nm node size. However, to go beyond 3nm will require new lithography processes.
With how quickly technology is advancing, it's possible to see more improvements to devices and the manufacturing process.
Featured image used courtesy of TSMC
Do you work in RF chip design? What trade-offs in size, performance, and power have you had to contend with? Let us know in the comments below.