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Andes Introduces RISC-V Out-of-Order Superscalar Multicore Processor

January 11, 2024 by Jake Hertz

The new CPU features the company’s first out-of-order architecture for higher instruction throughput, better performance, and faster processing speeds.

Although RISC-V had its humble beginnings as an academic project, the open-source instruction set architecture (ISA) is now an industry-wide movement consisting of hundreds of members who have developed high-performance IP. Adding to this momentum, Andes Technologies recently announced the general availability of its AX65 RISC-V-compliant CPU IP.

 

AndesCore AX65

AndesCore AX65 64-bit multicore CPU. Image used courtesy of Andes Technology
 

Let’s take a deeper look at the AX65’s performance, architecture, and design applications.

 

The AndesCore AX65

The AX65 is a 64-bit multicore CPU IP designed to meet the needs of application processor sockets of computing, networking, and high-end controllers. Compliant with the RISC-V RVA22 profile, the device includes support for RISC-V standard “G” extensions and is built around the company’s preexisting AndeStar V5 architecture. The CPU features a 13-stage superscalar out-of-order processor that supports up to eight cores with cache coherence. Notably, the CPU core includes extensive branch prediction features based on the Tagged Geometric Length algorithm, allowing for greater branch prediction accuracy.

 

A functional block diagram of the AndesCore AX65

A functional block diagram of the AndesCore AX65. Image used courtesy of Andes Technology
 

The device features up to 64 kB of Level-1 instruction and data cache and up to 8 MB of Level-2 unified cache. A dedicated cache coherence manager supports up to eight cores of cache coherence between L1 and L2 cache. Other features include a platform-level interrupt controller with up to 1,023 interrupt sources. 

The AX65 achieves speeds up to 2.0 GHz and an efficiency score of 9.25 CoreMark/MHz. Andes also claims that the device achieves a SPECint2006 score of 8.25 per GHz, which marks a 100% score improvement over the company’s AX45 family. 

 

What Is an Out-of-Order Pipeline?

Original CPU designs were built around the idea of an in-order pipeline, where the processor sequentially executes instructions one at a time. However, this method faced major inefficiencies, particularly when certain instructions would be stalled because data dependencies or cache misses clogged up the pipeline. 

To address these slowdowns, the industry adopted the out-of-order pipeline, which enables processors to execute instructions in a sequence differing from their original order. In an out-of-order pipeline, instructions are first fetched in order and then buffered into a pool where they await the allocation of resources. This pool enables instructions that are not immediately dependent on each other to be executed simultaneously as long as there are enough available resources (ALUs or memory paths). This process relies on dynamic scheduling algorithms and branch prediction units to properly allocate resources and anticipate future instructions and dependencies.

 

In-order (left) vs. out-of-order architecture

In-order (left) vs. out-of-order architecture. Image (modified) used courtesy of Cadence
 

By decoupling the instruction execution from the program order, the out-of-order pipeline enables much faster processing speeds. It minimizes idle time in the pipeline and allows for multiple instructions to be processed simultaneously. Out-of-order pipelines achieve a higher instruction throughput and better overall performance than traditional in-order pipelines.

While this method increases system complexity and power consumption in most cases, its performance gains have made it the norm in modern computing.

 

Andes' First Out-of-Order Processor

While the AX65 was announced months ago and has been evaluated by select customers since August, its general availability finally brings it to the masses. As the company’s first out-of-order processor offering, the AX65 may represent a big leap in computing for Andes Technologies. With the device achieving impressive CoreMark and SPECint2006 scores, the company hopes its new processor can be useful in high-performance applications like ADAS and networking.