SiFive, Co-Founder of RISC-V, Unveils Major Upgrades to RISC-V-Based Processors

July 25, 2020 by Vanessa Samuel

As the co-founders of RISC-V, SiFive's level-up on processors could have significant implications for custom SoC design.

SiFive recently announced its 20G1 release, an expanded portfolio of the company's RISC-V-based SiFive IP core processors. Some of the improvements SiFive focused on within this release were power, performance, and area (PPA).  

SiFive specializes in software automation tools that speed up the hardware development process. But this update to SiFive's RISC-V-based core processors is particularly relevant because of the company's history with RISC-V itself. Founded by the inventors of the world-renowned RISC-V ISA (instruction set architecture), SiFive may have a unique advantage in developing this technology. 


SiFive's History with RISC-V

As transistors became more expensive to design and difficult to scale, the inventors of RISC-V (reduced instruction set computer) decided it was time for a change. In 2010, they founded SiFive, which utilizes open sourcing and a RISC-V architecture along with customized silicon to reduce development costs and design time.


Evolution of RISC-V inventions

Evolution of RISC-V inventions, alongside SiFive inventions, from 2010 to 2017. Image (modified) used courtesy of SiFive

Initially, their goal was to publicize RISC-V widely. Now that the RISC-V architecture is world-renowned, the goal is to continually scale RISC-V. While the first tape out was 28 nanometers, SiFive now has hundreds of tape-outs, enabling a wider range of applications.


20G1 Upgrades Each Series Core

The SiFive Core IP 20G1 has introduced improvements within each of the different SiFive core series. The first major update is that each of the series cores has been upgraded with enhanced real-time capabilities.


Features of the 20G1 release

Features of the 20G1 release. Image (modified) used courtesy of SiFive

On the E3 and E7 Series, SiFive says the area has been reduced by up to 11% compared to the RV32I. The company also claims that within the U7 Series, performance is 2.8 times greater on the SiFive U74 (20G1) processor compared to the SiFive U74 processor (19.08).

This allows for improved data streaming for more applications, including AI. Power consumption has also decreased by up to 25% in the new SiFive U74 (20G1) processor, according to the press release. 


20G1 Builds on SiFive's Custom Silicon Tools

This SiFive 20G1 release follows several other company announcements that aim to enhance the scalability of RISC-V. These upgrades have also contributed to the rapid construction and shipment of chips.

For instance, SiFive offers the SiFive Freedom Tool suite, which contains SDKs, libraries, and other code to aid designers in customizing SiFive RISC-V processors. This database of tools is also located on the cloud for remote access.


SiFive's Freedom Studio

SiFive's Freedom Studio allows users to synchronize trace browsing. Image used courtesy of SiFive

SiFive Insight is another tool that assists with the customization process. It allows users to trace the execution of instructions by the processor step by step and observe the debug logs simultaneously. The SiFive 20G1 release is updated in SiFive’s Insight, which also supports Arm Coresight. SiFive asserts that Arm Coresight will make it easier for users to integrate with other SoC development environments. 

The SiFive 20G1 release has enhanced the cores of the SiFive Core IP line by lowering the power consumption, decreasing the area, and increasing the performance.  This option may be appealing to designers because of its free, open ISA and simplified templates for customizing silicon.



Have you ever used a RISC-V architecture? How did it affect your custom silicon design process? Share your experiences in the comments below.