Cisco Unveils ICs for AI Fabrics and Nvidia-Codeveloped USFP Optics Spec

Today, at the Open Compute Project (OCP) Global Summit 2026, Cisco and Nvidia announced a joint initiative to develop an open specification for Ultra-Dense Small Form Factor Pluggable (USFP) optical modules. Designed to support 400 Gb/s per lane electrical signals, the USFP specification aims to increase front-panel bandwidth density for next-generation Ethernet AI fabrics.

Concurrently, Cisco unveiled additions to its Silicon One ASIC family—including the Silicon One G302 ToR switch chip—along with scale-across routing architectures and runtime vulnerability shielding for Software for Open Networking in the Cloud (SONiC) environments.

The Interconnect Challenge: Scaling Beyond 200G per Lane

As artificial intelligence clusters grow to hundreds of thousands of GPU nodes, traditional networking infrastructure encounters strict physical constraints. Doubling cluster throughput by adding switch layers or increasing optical links increases latency, power consumption, and overall chassis complexity.

AI gains compound faster than infrastructure can scale.

To maintain rack-scale compute density without expanding the thermal or physical network footprint, interconnect designs must advance electrical lane rates beyond today's 200 Gb/s SerDes standards while keeping power dissipation within manageable thresholds.

Inside the USFP Pluggable Optics Specification

Developed jointly by Cisco and Nvidia in collaboration with TE Connectivity and Amphenol, USFP is designed as an open Multi-Source Agreement (MSA) specification. The form factor establishes a standard deployment path for 400 Gb/s-per-lane optical transceivers across AI switches and network interface cards. The two firms developed a module based on the new spec.

Cisco calls the USFP spec the industry’s first pluggable form factor designed for 400G SerDes lanes.

Key Technical Characteristics of USFP:

• Lane Configurations and Throughput: Initial USFP transceivers pack 16 full-duplex lanes into an OSFP-sized footprint, providing 6.4 Tb/s of aggregate capacity. The specification scales to 32 full-duplex lanes, enabling up to 12.8 Tb/s of total module throughput.
• Density and Efficiency Metrics: Compared to existing 200 Gb/s-per-lane pluggable optics, USFP delivers a 4x increase in front-panel bandwidth density and achieves approximately 1.3x higher power efficiency per bit transferred.
• Two-Dimensional Array Connector: USFP incorporates a 2D array connector utilizing a two-step insertion mechanism. High-speed electrical contacts engage only after the transceiver is fully seated within the cage, reducing mechanical contact wear, stabilizing insertion forces, and improving signal integrity for both 400 Gb/s and 200 Gb/s per lane operation.
• Thermal Management: The transceiver enclosure supports power dissipation up to 100 W without requiring embedded liquid cooling loops inside the module. This design simplifies chassis layout while remaining compatible with air-cooled and liquid-cooled system architectures.

In Cisco’s press briefing Rakesh Chopra, SVP, Silicon and Systems Architecture, Cisco Fellow, explained the significance of the new USFP offering. “This is actually the industry's first 400G per lane optics module,” said Chopra. “It comes in two different flavors: it comes in a x16 and a x32 form factor. That enables you to build a 6.4 Terabit or 12.8 Terabit optics module. If you compare that to where the industry is today, if we look at an OSFP 1.6T module, this enables a 4x bandwidth density increase than the leading solution today.”

In Nvidia’s own separate press briefing, Brian Sparks, Nvidia’s Senior Director of Ethernet and InfiniBand Marketing put the new module spec into perspective. Moving to 400G series doubles the per lane bandwidth, but only increases power by 1.5 X,” said Sparks. “So overall power efficiency gained is 1.3 X over 200G.”

Silicon One Expansion: From Front-End ToR to Deep-Buffered Routing

Cisco extended its unified Silicon One networking ASIC architecture, introducing new switching, routing, and management silicon variants optimized for AI fabric tiers.

Silicon One G302 Front-End ToR ASIC—Designed for top-of-rack (ToR) leaf switches, the Silicon One G302 provides 51.2 Tb/s of switching throughput. Integrating 256 x 200G SerDes lanes, the ASIC supports 1.6T OSFP optical interfaces and direct-to-chip liquid cooling integration. The chip optimizes how server nodes connect to front-end storage and compute management fabrics, with initial customer shipments scheduled before the end of 2026.

Silicon One G300 Shipping Status—The 102.4 Tb/s Silicon One G300 ASIC—tailored for back-end AI fabrics—has begun shipping in complete Cisco 8000 and Nexus 9000 series systems.

Cisco says its new set of ICs provide a complete AI Ethernet to optical architecture for scale-out cluster productivity.

Silicon One P200 Production Deployments—For inter-site scale-across fabrics, Cisco highlighted active production deployments of its Silicon One P200 ASIC. Featuring 51.2 Tb/s capacity, deep packet buffering, P4 programmability, and line-rate quantum-resilient encryption, P200 systems are deployed at scale in hyperscale networks, including Microsoft infrastructure and Alibaba's Quantum Cat router.

Silicon One A100L Out-of-Band Management—Cisco introduced the Silicon One A100L-powered Cisco 8001 management switch platform. Available in 10G and 1G port configurations, the system brings native SONiC support to out-of-band (OOB) rack management, standardizing API automation and recovery telemetry across the rack tier. Platform shipments are planned for Q2 2027.

Scale-Across: Inter-Site AI Networking

While traditional Data Center Interconnects (DCI) handle asynchronous, bursty CPU-to-CPU traffic, multi-site scale-across fabrics carry synchronized, high-bandwidth accelerator flows. According to Cisco, in a distributed training or inference topology, any packet drop, tail-latency spike, or optical link interruption stalls parallel processing loops across all participating GPU clusters, leaving compute nodes idle.

To address these requirements, Cisco presented a packet-to-light scale-across architecture combining deep-buffered P200 routing switches, 400G/800G ZR/ZR+ coherent pluggable optics, and open optical line systems (such as the NCS 1014 and Open Transport 3000). At OCP 2026 this week, Cisco and Keysight Technologies are conducting a live demonstration transmitting simulated GPU RDMA traffic across an 80 km optical link powered by P200 systems and coherent optics.

Live Protect for SONiC: Runtime Vulnerability Shielding

To address rapid vulnerability discovery and shrinking exploitation windows, Cisco announced Live Protect for Cisco-validated SONiC on Nexus 9000 switches.

Live Protect for Cisco-validated SONiC on Nexus One

Industry data shows the mean time-to-exploit (TTE) following CVE publication has dropped from 9.7 months in 2022 to approximately 10 hours in 2026. Live Protect injects runtime vulnerability shields into the management plane, control plane, network OS, and kernel.

By applying compensating policy controls directly to active systems, Live Protect neutralizes exploit vectors without requiring switch reboots or causing operational downtime, giving operators time to test and deploy software patches during scheduled maintenance windows. Live Protect for Cisco SONiC is scheduled for availability starting in mid-2027.

Open Stack Ecosystem Integration

Cisco outlined its support for open interfaces across all layers of the AI network stack:

• Silicon Tier: Support for P4 programmable pipelines, Switch Abstraction Interface (SAI), and active participation in the Ultra Ethernet Consortium (UEC) and OCP ESUN initiatives.
• System Tier: Multi-vendor interoperability compliant with Nvidia Network Cloud Reference Architecture (NC PRA) across Cisco 8000 and Nexus 9000 platforms.
• Optical Tier: Compatibility with OpenZR+, OIF, and OpenROADM standards.
• Network OS Tier: Operating options spanning community or Cisco-validated SONiC, FBOSS, custom NOS, NX-OS, and IOS-XR, with native SRv6 networking support.
• Control & Orchestration: OpenConfig APIs, Nexus One cloud-managed controllers, and CNCF-governed Cilium eBPF integration for Kubernetes cluster networking.

Together, these announcements appear to position Cisco as a leader in AI network evolution, spanning optical interconnect innovation, high-density switching silicon, resilient inter-site interconnects, and proactive software security.

As AI workloads demand unprecedented scalability and ultra-low latency across data centers, we can expect that Cisco's open architecture strategy and partnerships with industry leaders like Nvidia establish a comprehensive foundation for next-generation AI infrastructure.

All images used courtesy of Cisco.