With an Eye on Computing SoCs, Synopsys Combines IP Portfolio With TSMC’s 5nm Processes

May 13, 2020 by Gary Elinoff

Will the collaboration lower integration risks for designers?

Synopsys recently announced that it has combined its DesignWare IP portfolio with Taiwan Semiconductor Manufacturing Company’s (TSMC) 5nm process technology for computing SoCs. Synopsys’ DesignWare IP portfolio includes interface IP for a wide range of high-speed protocols and foundation IP.


DesignWare Foundation IP

Synopsys makes the Industry's broadest IP portfolio available for TSMC’s 5 nm process. Image used courtesy of Synopsys

According to the press release, this Synopsys-TSMC collaboration will allow the companies’ mutual customers to push their designs to the limits while lowering integration risk. 


An Ongoing Collaboration

The collaboration between Synopsys and TSMC was announced in September of last year. At that time, Synopsys achieved certification for many of its designs on TSMC’s 5 nm processes. Additionally, Synopsys’ design tools had also been certified on TSMC's N5P and N6 process technologies.

Suk Lee, senior director of the Design Infrastructure Management Division at TSMC, says, "Our close collaboration with Synopsys ensures a well-established design flow to help customers address the requirements on increasing complexities for their HPC and mobile designs and achieve their success of silicon innovations on 5-nanometer processes." 


A Powerful Alliance

TSMC—the world’s largest foundry and a major Apple supplier—is presently being solicited by the Pentagon to open a US chip factory. TSMC’s 5 nm technology is optimized for both high-performance computing applications and for mobile applications, where low power requirements are key.


One of TSMC’s 5 nm production facilities in Taiwan

One of TSMC’s 5 nm production facilities in Taiwan. Image used courtesy of TSMC


Synopsys’ IP accelerated initiative includes a range of support, including IP prototyping kits like the HAPS-70 FPGA-based prototyping platforms.


New Offerings for Computing SoCs

The announcement highlights some of the new offerings made possible by the collaboration, they include:  

  • DesignWare’s Interface PHY IP portfolio, which includes die-to-die, PCIe 5.0, CXL and CCIX, interconnects, and 112G/56G Ethernet
  • High-Performance Memory Interface Solution IP for DDR5, LPDDR5, and HBM2/2E 
  • Die-to-die PHYs for 112G ultra short-reach (USR) and extra short reach (XSR ) connectivity for reliable links, yielding extremely low latency
  • Foundation IP, including low-power logic libraries, multi-port memory compilers, and TCAMs 

According to John Koeter, senior vice president of marketing and strategy for IP at Synopsys, their move to offer the DesignWare IP on TSMC's 5 nm process will help both companies' customers "speed development for a new era of high-performance computing SoCs."


Designware's Legacy 

Synopsys has long been a provider of silicon-proven IP solutions for SoC designs. To accelerate the design process, including everything from prototyping, software development, and finally the integration of IP into SoCs, the company offers IP software development kits, IP prototyping kits, and IP subsystems.


DesignWare IP prototyping kits help designers implement IP in a SoC

DesignWare IP prototyping kits help designers implement IP in a SoC. Image used courtesy of Synopsys

Perhaps most importantly, Synopsys says it offers customers extensive support, reducing the risks involved in integration and ultimately empowering OEMs to get their products to market faster.


Faster Development of SoCs for AI

DesignWare’s Interface and Foundation IP for TSMC's 5nm process technology is scheduled to be available in late Q2 of 2020. 

Both companies hope that this move will help engineers involved in designing and manufacturing SoCs for AI, high cloud computing, or networking and storage applications to bring high-quality products to market.


Featured image (modified) used courtesy of Synopsys


Do you work with SoCs for AI? What obstacles do you face in the prototyping process for such systems? Share your thoughts in the comments below.