The instruction set architecture (ISA) is truly a place where software and hardware meet: it’s an abstraction that describes how a processor can be programmed to perform certain actions, using machine code. This article explores some of the history behind how ISAs were developed.

At the lowest level, instructions are provided in binary, describing everything from addressing modes, registers, memory layout, interrupt and exception handling, I/O, and of course, instructions for the processor (ADD, SUB, etc).

The advent of the ISA has helped bring the cost of computers down—since the same ISA can be used in compatible processors, without having to re-invent the wheel each time. With less time and resources spent on the ISA, more time can be spent on application and improving other aspects of computing. Today, licensing ISAs is common. 

ISAs come in several different flavors. Many are proprietary (think AMD), while others are paving the way for open source (think RISC-V). To help get a feel for what’s out there, here’s a brief primer on the history, evolution, and characteristics of a select few ISAs, starting with those developed by Digital Equipment Corporation (DEC). 

DEC was a computer systems vendor that operated from 1957 until its eventual acquisition by Compaq in 1998. The company was best known for its minicomputers, the PDP and the VAX, and was one of the most successful tech companies of the time. Part of DEC's legacy is in its ISAs, such as VAX, Prism, and Alpha.

 

DEC founder, Ken Olsen, in front of the company headquarters that was founded inside an old mill. Image courtesy of Boston.com.

 

VAX (1977)

VAX, which stands for “Virtual Address eXtension”, was developed by DEC in the 70s for their VAX minicomputers. It first appeared in the VAX-11/780 in 1977. 

VAX was a 32-bit Complex-Instruction-Set-Computer (CISC) ISA designed for DEC’s VMS operating system. CISC was a way of abstracting assembly language programming into a more intuitive set of instructions. The VAX ISA is cited as being the birth of CISC by some computer historians. The VAX ISA challenged the idea that high-level compilers could not produce the same quality of assembly language programming done by an actual person.

 

The VAX-11/780 computer. Image courtesy of the Computer History Museum.

 

The success of the VAX ISA is probably most evident in the fact that the performance of VAX-11/780 became a benchmark for CPU performance—the term “VAX Unit of Performance” (VUP) was coined, and so a system 10 VUPS would be 10 times faster than a VAX machine.

Some features of VAX include:

  • Virtual addressing
  • Orthogonal Instruction Set (any instruction can be used in any addressing mode)
  • Register masks
  • 16 general purpose registers
  • An expansive selection of addressing modes including: literal, immediate, load effective, register/register deferred, postincrement/predecrement, displacement/displacement deferred, indexed, and several combinations of the above
  • Instructions such as ADD, COMPARE, IN, JUMP IF, etc 

For more information, see the VAX ISA Reference Manual.

 

Prism (1988)

Prism was a research project that DEC began in 1982. By this time, the Reduced-Instruction-Set-Computer (RISC) ISA was becoming a new, competing standard, and so work into a high performance, competitive 32-bit RISC ISA became a new goal of the company. Prior to Prism, DEC had four other projects for RISC ISA development: SAFE, Titan, Cascade, and HR32. Of the four, only SAFE proposed a 64-bit ISA.

Prism’s original design was for a 64-bit system, but ultimately designers chose 32-bits, with extensions for vector instructions and 64-bit registers. A feature called epicode (extended processor instruction code) which also exposed further special instructions.

Two derivatives of Prism would also be developed, including MicroPrism for CMOS based microprocessors, and Crystal for ECL based systems.

In 1988, Prism was canceled due to internal disagreements on the focus and direction of DEC against increasingly competitive business adversaries. The in-house developed ISA was abandoned for off-the-shelf options in order to try to stay competitive in the workstation market.

 

Alpha (1992)

The Alpha ISA, also know as DEC Alpha or Alpha APX, was first introduced in 1992 and used until 2007. 

Alpha is a 64-bit, RISC-based ISA that is based off of the 32-bit Prism ISA project. The changes made in Alpha, compared to Prism, largely centered around the ability to support the VMS operating system, and the fact that many RISC-based ISAs were now being implemented in 64-bit. It also had to be backward compatible with the VAX ISA used in previous DEC microprocessors.

Alpha was developed for high performance systems, and the microprocessors it was implemented in broke many firsts: the Alpha 21064 CMOS based microprocessor had an operating frequency that was competitive against ECL based mainframes; Alpha 21164 was the first microprocessor to have a secondary cache on chip; and Alpha 21364 had the first on-chip memory controller.

 

The Alpha 21164 chip, manufactured by Samsung. Image courtesy of ChipdB.

 

Alpha was discontinued after a series of events saw DEC being sold to Compaq in 1998. Compaq was using Intel chips, sold the Alpha IP to Intel where it was discontinued. The last Alpha-based systems continued to be sold by Hewlett-Packard, which bought Compaq, until 2007. 

Features of Alpha include:

  • 32 integer registers (R0-R31), 32 floating point registers (F0-F31), floating point control register (FPCR), 2 lock registers (LR0-LR1), and a program counter
  • Data types: quadword (64-bit), longword (32-bit), IEEE T-floating-point (64-bit, double precision), IEEE S-floating-point (32-bit, single precision), VAX G-floating-point (64-bit, double precision), VAC F-floating point (32-bit, single precision)
  • Six 32-bit instruction formats 
  • Logic, arithmetic, and control instructions
  • Four extensions: Byte-Word Extension (BWX), Motion Video Instruction (MVI), Floating-Point Extension (FIX), and Count Extension (CIX)
  • To maintain high-speed performance features like branch delay, suppressed instructions, and byte load/store instructions were eliminated 

For more information see the Alpha Instruction Set Specifications.

 


 

We'll be covering the history of other ISAs in the future. What would you like to know when it comes to ISAs? Share your thoughts in the comments below.

 

Comments

9 Comments


  • tomtmook 2018-08-08

    Do you consider the instruction set for Intel’s current manifestation of the Pentium, the i3, i5, i7, etc, to be different than the instruction set for the original 80386? 

    The 80386 came out in the late ‘80s.  It did not have internal cache RAM nor did it have an integrated math coprocessor.  Over the years and with successive generations, Intel has added on chip cache RAM and math coprocessor.  They’ve tweaked the architecture to allow faster memory and add-on card access (PCI bus and its derivatives).  They have glued cores together to allow parallel processing.
    But…
    ...it’s still based on the 1980’s generation 80386.  The instruction set is largely the same.  Essentially they’ve improved the ‘386 by adding cache, adding bridges, widening the bus and improving clock speed and throughput, but deep down it’s still an 80386!

    • Wuerstchenhund 2018-08-15

      It isn’t, really. There’s a lot more from the 80386 to modern intel processors than the few things you listed. The big break came with the P5, the first superscalar intel x86 processor, and when the P6 came out the underlying processor had more in common with a contemporary RISC processor than the CISC approach of the 386.

      Saying a modern intel processor is deep down still a 80386 is the same as saying a Tesla car is deep down still horse and buggy wink

  • jing-hu wang 2018-08-20

    What was machine using Alpha 21364 chip?

  • Richard Tomkins 2018-08-24

    The VAX 11/780 and VAX 11/750 Instruction Set were loaded at power on. It was microcode. The micrcode formed the VAX Instruction Set. I wrote a micrcode program for a VAX 11/750 that was installed at boot time, replacing the complete VAX Instruction Set and enabling to test memory circuitry in the system. In this fashion I could toggle specific bits in the memory interface and troubleshoot the system to the chip level.
    The 11/780 was a wicked fast COBOL engine at the time, as the microcode load was a COBOL instruction set. Thus, when the machine executed COBOL, it did so at the VAX COBOL instruction set level and this made the code, oh so much faster. Business system users were enamored with the performance at the time.

  • Richard Tomkins 2018-08-24

    Alpha Instruction Set was not backward compatible with VAX Instruction Set.
    The developers created a Binary translator to convert much of the VAX Binaries aka, VAX Binary Instructions directly into Alpha Instructions.

  • Richard Tomkins 2018-08-24

    Although you have touched upon some of the highlights of some of the DEC processor Instruction Sets, your overview is very light.
    Other than IBM, no other company has ever gone to the synchronous depth of hard and software engineering that DEC went to.
    The VAX Instruction Set was a DEC Standard and thus subject to the control of the CEO (Chief Engineers Office). Each and every iteration of microcode for each and every VAX instruction was under tight ECO (Engineering Change Order) control.
    All DEC VAX computers could and di participate in VAXclusters, this was only ensured by all processors executing the VAX Instruction Set identically to every other cluster member, no matter what VAX processor was being used.
    The significance of this may escape many, but in essence, all VAXcluster members booted from a single OpenVMS binary on a single disk. Yes, each processor had unique configuration elements as defined by its capabilities, speed, memory size, work load and other factors, but they all used a single system. Later with the introduction of the Alpha, there were two disks, one with OpenVMS Alpha binaries and another with OpenVMS VAX binaries, yet, all these different processors and those with a completely different Instruction set all participated in a Cluster.
    When we added VAX Fault Tolerant systems to our portfolio, rather than then software approach as most other manufacturers did, we took a more involved hardware approach. A specific chip was designed to interface multiple processors, memory units, disk interfaces, network and I/o, just like it was done in Telephony. To enable this functionally during boot, a small binary load was added. With the resulting system, I could pull memory cards and processor cards from the machine while it was running without and problems at all. Same for disks and juggling network connections and power cords. Bullet proof computing, even in a cluster.
    As to Intel, man, those guys ...
    At the time, DEC made the hardware that made semiconductor devices. We developed the technology and then sold it to others, including Intel. When Intel CPU clock speeds started to appear with heretofore unheard of clock speeds, everyone knew that something was up, after all, we had not yet sold them the latest and greatest semiconductor manufacturing technology. After much investigation, it was shown that they had copied something like 12 or 14 patented processor designs from DEC. Some of these were branch prediction, predictive execution and a myriad of others. Apparently what was so interesting about the whole process was that the actual semiconductor designs were identical in layout to that used in Alpha chips, as it was told to me. Which would indicate that they had dissected chips and copied the gate layout. DEC won the lawsuit and imposed heavy penalty on Intel. From what I was told, they had to buy the newly completed Fabrication facility and take on all the employees too and be ready to exclusively make Alpha chips when the order came through. At the time, DEC had IBM contract manufacturing all the Alpha chip production, so Intel had a Fab facility, filled with really top notch staff that pushed brooms and played cards all day for more than a year. I am convinced that the Compaq purchase of DEC was a plot by Compaq and Intel to get Intel out of its obligation as within the first week of Compaq’s acquisition of DEC, Intel was released from the IP infringement obligations.
    Of course, all that, could simply be a great story of high technology skullduggery and intrigue.

    • Richard Tomkins 2018-08-25

      I should say that I have no direct knowledge of Intels penalty for copying DEC IP, I am recalling hearsay.
      What I forgot to highlight about VAX Fault Tolerant systems, was that all applications running on one of these systems was fault tolerant as it did not need to be linked with special libraries to make it so.

  • alderson 2018-09-19

    DEC was known for far more than the PDP-11 and VAX. Wait, you have conflated 6 instruction set architectures, by referring to them generically as “PDP”!

    DEC built several successful lines of computers under the rubric “PDP-n” for small integers n, but they fall into several distinct families:

    PDP-1: 18 bit word addressable, 6 bit instruction
    PDP-4/7/9/9L/15: 18 bit word addressable, 5 bit instruction, upwards compatible from PDP-4 to PDP-15
    PDP-5; PDP-8; PDP-8/i,l;  PDP-8/e,f,m; PDP-8/A; DECmate, DECmate II and DECmate III: 12 bit word addressable
    PDP-6, PDP-10, DECsystem-10, DECSYSTEM-20: 36 bit word addressable, several clone manufacturers
    PDP-11 (couple of dozen models): 16 bit byte addressable
    LINC-8 and PDP-12: PDP-8 compatibles which also executed code for the LINC computer from Lincoln Labs
    PDP-14, PDP-16: Register Transfer Module build-to-application systems

    DEC built hundreds of 18-bit computers, tens of thousands of 12-bit computers, thousands of 36-bit mainframes, and hundreds of thousands of 16-bit computers. They should not all be lumped together as a generic “PDP”.

    As for the VAX and the PDP-11, the original models of the VAX-11 (as it was originally designated) had a mode bit which would turn them into expensive PDP-11 systems. The earliest version of the VMS operating system and utilities made use of this fact. Later models dropped this compatibility mode, along with the “-11” in the system name.

    On the Alpha, VMS made use of a (software) feature called VEST, which automagically compiled VAX code into Alpha code at runtine; on modern VMS systems running on Intel Itanium processors, a similar feature called AEST does the same thing for Alpha code. Neither Alpha nor Itanium has a “VAX compatibility mode”; it’s all software.