MCU Carves Power Domains to Optimize CPU Load, Data Transfers

October 31, 2016 by Majeed Ahmad

ST's new microcontroller is raising processing levels while boasting three power domains for energy efficiency.

ST's new microcontroller is raising processing levels while boasting three power domains for energy efficiency.

It's a familiar quandary. How can we raise the bar in processing and add on-chip resources like memory and peripherals in a microcontroller while keeping power consumption in check?

That's a key consideration for MCUs employed in a new breed of Internet of Things (IoT) applications like industrial gateways and home automation that mandate greater memory density and richer analog and connectivity peripherals.

At the 2016 ARM TechCon held in Santa Clara on October 25-27, STMicroelectronics demonstrated its new STM32H743 microcontroller that features ARM’s highest-performing Cortex-M core. It uses three different power domains to optimize the CPU load and data transfers. The microcontroller is based on the ARM® Cortex®-M7 core running at 400MHz and consumes less than 280uA/MHz in run mode and 7uA in standby mode.


The block diagram of STM32H743 microcontroller illustrates the memory and peripheral integration. Image courtesy of STMicroelectronics.

Communication and IoT Security

STMicro claims this is the first microcontroller built on the 40nm node geometry, and that enables it to further improve memory density and thus ease code storage and firmware constraints that are common in high-end embedded systems. The STM32H743 microcontroller boasts 2MB of dual-bank Flash and 1MB SRAM embedded memories.

Next up, STMicro's new microcontroller lines up 11 analog peripherals for devices ranging from 14-bit ADCs to comparators and timers to op amps. It features 35 communication peripherals supporting the existing standards such as Ethernet, SPI, and UART as well as new connectivity standards like TT-CAN and FD-CAN.

Security is a key ingredient in the IoT recipe; at the opening keynote at the ARM TechCon, Masayoshi Son, CEO of the Softbank (ARM's parent company), called the IoT a dangerous proposition without security. ARM's chief executive Simon Segers also tied the demand for intelligent silicon to different levels of security.

Here, the STM32H743 microcontroller provides cryptographic and hashing accelerators for secure communications. Moreover, it offers provisions for secure key storage to ensure production security against cloning attempts and field security for tamper prevention.

Performance and Power Metrics

ARM's Cortex-M7 core is currently leading in the DMIPS/MHz, DSP, and FPU benchmarks, offering 2.14 DMIPS/MHz and 5 CoreMark/MHz. More Dhrystone Million Instructions Per Second—or DMIPS—means less time in processing and more energy savings. This is an industry-standard benchmark for general processor performance.

Likewise, CoreMark is a standard benchmarking framework managed by the Embedded Microprocessor Benchmark Consortium (EEMBC). According to Frederic Le Cam, ST's Marketing Product Line Manager for the Microcontroller Division, ST's new MCU is carrying out three levels of optimization to ensure power efficiency while attaining higher performance levels.


The STM32 family of MCUs ensures energy efficiency through a multi-power domain architecture. Image courtesy of STMicroelectronics.

First, the STM32H743 microcontroller employs a dynamic voltage scaling technique to adjust power consumption according to performance demands.

Second, it makes use of the batch-acquisition mode to capture data directly into memory without waking up the CPU core from energy-saving mode.

Third, the MCU creates multiple memory domains and each domain can be powered on or off independently to maximize energy savings. These memory domains—created while using ST's Dynamic Efficiency energy-saving technology—can be reactivated by programmable events.

Le Cam said during the demo that the high processing domain D1 is dedicated to compute-intensive tasks and high-data bandwidth streams interconnected through a high-performance AXI bus matrix: "The connectivity tasks domain D2 provides a rich set of peripherals, DMAs, and memories on AHB bus matrix for independent transfers." 

"The third domain D3 utilizes the batch-acquisition mode, as mentioned above, to provide peripherals, DMAs, and memory for continuous tasks," Le Cam concluded.