Micron Unveils 1α DRAM Process Node—the Highest-Density DRAM to Date

January 27, 2021 by Jake Hertz

Micron claims to have broken the glass ceiling of the 1z DRAM node with a new process that improves memory density by 40%.

DRAM has been scaling notably slower than many of its other silicon counterparts. While microprocessors have been fabricated all the way down to the 5nm node, DRAM is still stuck in between the 20nm and 10nm node and has been since about 2016. Theoretically, the 10nm is the limit for DRAM. 


DRAM scaling trend up to 2018

DRAM scaling trend up to 2018. Image used courtesy of Tech Insights

Because of this, manufacturers have created a new process node-naming scheme that refers to the dimension of half of the pitch of the active area in the memory cell array. The convention is as follows: 

  • 1x nm: 19nm–17nm (Gen1) 
  • 1y nm: 16nm–14nm (Gen 2) 
  • 1z nm: 13nm–11nm (Gen 3) 

To this point, manufacturers have only reached the 1z “node.” Now, Micron Technologies has become the first company to bring the next smallest dimension DRAM, 1α, to the market


Capacitor Aspect Ratio and DRAM Scaling 

There are a multitude of reasons that scaling DRAM has not been as straightforward as scaling microprocessors (if you consider that a straightforward process).


A single DRAM cell

A single DRAM cell consists of a pass transistor and a storage capacitor. Image used courtesy of Blocks & Files

One of the reasons involves the very nature of DRAM; it requires a storage capacitor to hold values. Because a device’s capacitance is directly related to its physical dimensions, shrinking a capacitor laterally will reduce its effectiveness. Not only will the capacitor no longer be able to hold a measurable charge but it will also leak charge more quickly, requiring more dynamic refreshing. 

Some industry suppliers argue that a major development in materials will be necessary to sufficiently overcome this challenge. 


Fabrication Challenges and DRAM Scaling 

Another limiting factor to DRAM scaling involves challenges in fabrication

Silicon processing often relies on photolithography to etch detailed patterns into the semiconductor. The photolithographic design requirements of DRAM cells, specifically the intricacies of the capacitors, makes for a very difficult manufacturing process.


Micron's DRAM roadmap continues to unfold

Micron's DRAM roadmap continues to unfold. Image used courtesy of Micron

As the features shrink, photolithography is limited by the Rayleigh criterion. This criterion states that it’s impossible to use photolithography to etch a feature less than roughly half the wavelength of the light being used. This means that when features are etched small enough, it becomes virtually impossible to create DRAM cells that are accurate enough using conventional techniques. 

Some challenges include patterning the capacitor holes with good alignment and creating capacitors with accurate aspect ratios for predictable behavior.


Micron Introduces a New Memory Process Node

While these challenges have made progress staggeringly slow, some suppliers are still making progress. Micron is the first company to make significant progress recently, yesterday becoming the first company to bring the 1α process node to volume production. 

Unlike some companies that are looking toward extreme ultraviolet (EUV) lithography as the solution, Micron achieved downscaling via "multiple patterning." The idea behind this technique is to improve resolution by adding non-lithographic steps to create multiple, small features out of a single larger feature.


Multiple patterning process

Multiple patterning process. Image used courtesy of Lam Research


Micron engineer Thy Tran explains, “Oversimplifying quite a bit, the basic idea is to create sacrificial features using the stepper, coat the sides of those features with a different material, and then remove the original sacrificial features. Voilà—two half-size features! Repeat the process and we have four features of the size we need for 1α.” 


A 40% Bump in Memory Density 

This news is significant in the memory space, considering Micron’s new 1α DRAM offers a 40% improvement in memory density over its previous 1z DRAM node. Micron also claims that the new technology offers up to 15% power savings compared to 1z mobile DRAM. 

According to the company, the 1α node will be distributed across its DRAM product portfolio this year to support all environments that use DRAM today.