NXP Debuts i.MX 95 Armed with 3D Graphics and NPU Improvements

We continue our coverage of CES this week, this time with today’s reveal by NXP Semiconductors of the i.MX 95 family, a new addition to the company’s i.MX 9 series of applications processors. The devices combine several high-performance compute elements, including advanced 3D graphics, neural processing, embedded security, and more.

The device expands NXP’s i.MX 9 series, which includes the i.MX 93 announced back in November. In this article, we examine the features and specs of the new i.MX 95 applications processor and share analysis from our interview with James Prior, product manager for NXP’s Advanced Edge Processor Innovation Team.

 

Part of NXP’s i.MX 9 series of applications processors, i.MX 95 adds new NXP-developed NPU and ISP cores to the mix. Image used courtesy of NXP

 

Prior says that the company doesn’t see the 9 series as necessarily replacing NXP’s earlier i.MX 8 processor series, but more as interleaving and augmenting the 8 series in order to provide a broad portfolio offering to the market.

 

An Architecture Designed for Flexibility

According to Prior, the key aspect of the i.MX 95 architecture is its flexibility. The processor's main CPU domain consists of up to six Arm Cortex A55 CPU cores arranged in a coherent cluster. But there’s also a separate domain with a real-time Arm Cortex M7 MCU. In addition, there’s a low-power real-time domain powered by a low power (safety) Arm Cortex M33 CPU.

“All this is linked together with what we call our Flex Domains,” says Prior. “These allow engineers to mix together which pieces of IP they want to use in a particular domain.” In other words, the main CPU domain can use all of the chip’s functions and features (see image below). But also the real time MCU can be connected to different on-chip elements as well. “They're very flexible, not only for us on a product definition side, but from the customer side for their implementation,” says Prior.

 

The i.MX 95 block diagram. Flex Domains enable developers to have different compute elments use a variety of peripherals and functions. Image used courtesy of NXP (Click image to enlarge)

 

Rich Multimedia Resources on Chip

Meanwhile, there’s a lot going on in the i.MX 94’s ML (machine learning) and Multimedia block. This domain includes an Arm Mali 3D GPU core, but also an independent 2D GPU with a real time blend engine.

“This means we can overlay the graphics from the 2D GPU on anything that's in part of the vision processing pipeline, whether that's an external network device, a directly connected camera, or output from the 3D GPU,” says Prior. “All of that can be blended and presented.”

Prior says that the i.MX 95 is NXP’s first applications processor to support LPDDR5 DRAM, enabling increased bandwidth and future-proofing. But the device also maintains compatibility with older LPDDR4X DRAM because not everyone is using LPDDR5 yet. The i.MX 95 also supports memory encryption and in-line memory correction.

The i.MX 95 also integrates a new image signal processor (ISP) developed by NXP. According to Prior, the  ISP is optimized for machine vision applications and supports two "Regions of Interest." The ISP can also do HDR combination of two exposures and advanced de-noising and edge enhancement with support for color, monochrome and RGB-IR camera sensors.

 

NPU Core Scheme Enables Scalability

Another key element in the i.MX 95 processor architecture is the device’s embedded NPU. The i.MX 95 family is the first i.MX applications processor family to integrate the NXP-designed eIQ Neutron NPU (neural processing unit). NPUs are not new to NXPs’ chip designs. In fact, NXP’s recently released microcontroller, the MCX-N, embeds an NPU.

We asked Prior what the NPU on the i.MX 95 has in common with the NPU on that microcontroller. “It's the same but different,” he says.”It's the same core IP and design, but the one on the i.MX 95 is the high end instantiation.” But while the performance levels are different, they share a common basic architecture with support for all the same major neural network structures (CNN, MLP, RNN, LSTM, TCN, and more). That lets engineers use NXP’s eIQ software development environment on both devices.

 

The i.MX 95 processor’s embedded NPU uses the same basic hardware architecture as the NPUs in lower end NXP devices, allowing users to scale up as needed. Image used courtesy of NXP

 

“We got a lot of feedback from the market,” says Prior. “Engineers who are adopting AI/ML want scalability and they want consistency. And we've been handling that with our eIQ ML software development library. Bringing in a common hardware platform underneath increases scalability and reduces the amount of re-development that needs to be done." The NPU hardware scales from performance efficient 32 Ops/cycle to 2k Ops/cycle and beyond, he says.

 

Long Life Support

To serve the needs of embedded applications, the NXP says that all i.MX 8 series and i.MX 9 series products are guaranteed for a minimum of 15 years of availability because they are part of the NXP product longevity program. More information about the iMX 95 is available in the i.MX 95 fact sheet. The company says its i.MX 95 applications processors are expected to begin sampling for lead customers in 2H 2023.