Researchers Unveil Liquid-based Memory Concepts for Mass Storage

Driven by the rising demand for compact electronic devices, there is a significant growth in the semiconductor memory market. This is especially true for NAND flash memories, as mass storage technology transitions from hard disk drives (HDDs) to solid-state drives (SSDs). For modern processors, the ability of memory to move large amounts of data around at high speeds is vital. Without this ability, processors can't perform at their full potential.

Among all the memory technologies, NAND flash is the most used online and nearline storage technology because it offers the lowest latency and power consumption. Researchers have improved the bit density of NAND flash storage solutions consistently throughout the years. However, this scaling of NAND flash is expected to slow soon.

 

NAND flash is the leading technology for today's SDDs, such as this Crucial P3 Gen3 NVMe SSD. Image used courtesy of Crucial by Micron

 

As the scaling of NAND flash memories is starting to saturate, new storage concepts are being investigated, including Phase Change Memory (PCM), Resistance RAM (ReRAM), Ferroelectric RAM (FRAM), Magnetic RAM (MRAM), Spin Transfer Torque MRAM (STT MRAM) and carbon-nanotube memory (NRAM). These new technologies can replace and complement the existing storage solutions in terms of latency and bit density.

Offering some alternative approaches, IMEC researchers propose two new liquid-based storage concepts for ultra-high density nearline storage applications. These new solutions could make archived data like emails, multimedia, and other large documents available to the user within seconds. IMEC is an R&D hub for nano- and digital technologies.

 

Scaling Challenges of NAND Flash Memory

In a NAND flash memory, floating-gate transistors are connected in series, and the bit line is pulled low only when all the word lines are high. All these memory cells are organized in two or three-dimensional arrays at the cross-point of words. An access device—usually a transistor—connects the storage element to wires needed for reading and writing the memory cell. Despite these additional transistors, the reduction in ground wires and bit lines allows for higher bit density and storage capacity.

However, this configuration with one access device for each storage element limits the bit density. In HDDs, fewer access devices are connected to a relatively large memory array, allowing for higher bit densities and lower cost per bit than NAND flash memories. But they are slower and less power efficient because of the mechanically attached reading mechanism.

By considering the advantages of both these technologies, new concepts can be found for making ultra-high-density memories.

 

IMEC's Liquid-based Memories

IMEC researchers propose two new liquid-based memories for nearline storage: colloidal and electrolithic memory.

The colloidal memory consists of a colloid of two or more types of nanoparticles inside a reservoir. The reservoir is attached to capillaries, where the nanoparticles are inserted. The information is encoded in the form of a sequence in which the particles are entered into the capillaries. The nanoparticles can be selectively impacted by electrodes located at the entrance of each capillary. A CMOS circuit controls the array of electrodes and addresses each electrode individually.

 

Illustration of the colloidal memory concept. Image used courtesy of IMEC

 

For this concept, researchers explore dielectrophoresis as a writing mechanism, where an alternating electric field across the electrode exerts a force on the nanoparticles. The nature of the force (attractive or repulsive) depends on the type of nanoparticle and the frequency of the electric field. The researchers suggest that a selective writing process can be created by applying different frequencies.

 

Diagram of the electrolithic memory concept. Image used courtesy of IMEC

 

Just like the colloidal memory, the electrolithic memory makes use of a fluid reservoir and an array of capillaries. Here, metal ions are dissolved in liquid. For this concept, there are several ways to encode the information. The researchers report that one possibility could be that 1 nm of a metal ion can be used to encode 0, while 2 nm of an ion can be binary 1.

The IMEC researchers fabricated an electrolithic memory with parallel nano wells of 80-150 nm diameter and 300 nm depth as arrays. They successfully demonstrated the read and write ability of memory using mm- and μm-sized electrodes.

 

Proof of concept of the electrolithic memory. This shows microelectrode arrays with electrodes of different sizes in the mm- to µm range. Image used courtesy of IMEC

 

Industry Adoption of Liquid-based Memories

The new liquid-based memories are in the exploratory research stage, especially the colloidal memory. The IMEC researchers are currently working on fine-tuning the concept and providing the first proof of principle of the colloidal memory on a nanometer scale.

The researchers believe that scaling efforts in these technologies can make them comparable to 3D NAND flash. However, for that, the researchers must be able to make capillaries with aspect ratios of about 400:1 and 165:1 for colloidal and electrolithic memory, respectively. Moreover, to become a viable commercial storage solution, the technology must have optimal response time, bandwidth, read and write endurance, energy consumption, and lifecycle. The IMEC researchers are planning to perform these evaluations in further research.