Startup Knocks Down Chiplet Hurdles with High-performance Link
Eliyan is emerging from stealth mode, unveiling the successful tapeout of its high-performance UCIe-compliant die-to-die interconnect technology in 5 nm process.
By and large, one of the most notable trends in the computing industry today is the move towards chiplets. Promising a way to continue performance gains offered by heterogeneous devices like SoCs, chiplets have recently found themselves in product offerings ranging everywhere from Apple to NVIDIA.
Seizing on the momentum, startup Eliyan is now coming out of stealth mode and bringing with it some exciting technology. Today, Eliyan announced a successful round of funding as well as the successful tapeout of its technology on a 5 nm process.
The Eliyan founders see a need for highly efficient die-to-die (D2D) PHYs to link chiplets with different functions in one package. Image used courtesy of Eliyan
AllAboutCircuits had the chance to talk with Ramin Farjadrad, Syrus Ziai, and Patrick Soheili, all founders of Eliyan, to hear about the company and the news firsthand.
The Rise of Chiplets
One of the most powerful trends in the computing industry today is the move toward chiplet-based designs.
In search of higher-performance computing, the system-on-chip (SoC) has become one of the most popular computing platforms available. The idea behind SoCs is to create a heterogeneous system that integrates as much computing functionality as possible into a single piece of silicon.
However, as SoCs have continued to grow in size, they are approaching the die reticle limit, which is the maximum chip area that can be exposed to a single photomask during manufacturing.
The solution to this has been the introduction of chiplets, consisting of individual silicon that shares a single package and is connected together through some interface. “The chiplet era means that you go from an SoC that is limited in size, you break every function to separate chiplet and then connect them together,” says Farjadrad. “In this way, you do not have the issue of a single chip being too big to be manufacturable.”
Chiplet design with an interposer. Image used courtesy of Jinwoo Kim and co-authors
Recently, the main interface technology used between chiplets has been a silicon interposer, which is a silicon substrate that provides a high-bandwidth interconnect between each die. However, this technique is far from perfect.
“The Silicon interposer is the main way of chiplet integration today, but it comes with a number of disadvantages,” says Soheili. “Specifically, they are still limited by size and cannot be manufactured too large. Additionally, to connect to the silicon interposer, chips are designed with microbumps. These microbumps cannot be fully tested at a safer level before integrating as part of this package, which becomes a yield issue.” Further, thermal considerations limit clock rate and ultimately performance.
Eliyan’s Chiplet Technology
Instead of traditional silicon interposer technology, Eliyan is now emerging from stealth mode with two unique chiplet technologies.
Their first technology is called NuLink and is a high-performance die-to-die PHY solution for chiplets. Leveraging concepts from Farjadrad's Bunch of Wires (BoW) scheme, which has been adopted by the Open Compute Project (OCP), NuLink’s technology is a backwards-compatible superset of UCIe/BoW that aims to enable advanced packaging without the downsides of silicon interposers, says Farjadrad.
“NuLink is a high-performance solution that provides similar bandwidths, power, and latency as a silicon interposer, but it lets you use an organic package.”
NuLink enables the direct use of an organic substrate. Image used courtesy of Eliyan
As good as this may be, a major challenge still remains that Implementing high-speed PHYs in slow memory processes is not very practical. To address this, Eliyan introduces its second technology, its NuGear 2.5/3D topology.
NuGear is a topology that acts as an adapter to connect off-the-shelf chiplets with microbumps over an organic substrate with standard bumps. The scheme is offered in both 2.5D and 3D topologies and ultimately serves to remove the need for a silicon interposer without modifying the high-memory bandwidth (HMB) base die.
“Basically if you magically put NuGear on both sides, you all of a sudden get a solution which provides all of the benefits of a high bandwidth die-to-die PHY without the traditional drawbacks,” says Ziai.
NuLink shown with NuGear. NuGear (formerly called Gearbox) can be offered in both 2.5D (above) and 3D (below) topologies. Image used courtesy of Eliyan
According to the company, the combination of NuLink and NuGear enables a larger system-in-package with 4x more HBM per package and a 20% higher clock rate, ultimately leading to a 10x performance improvement. More HBM per package also eliminates the need for power-hungry ASICs, resulting in power savings on the order of 5x at the same performance.
First Silicon in Q1 2023
As a testament to the viability of Eliyan’s technology, the company has made two significant announcements today.
First, they have officially closed its Series A funding round which came in at $40 million. Second, they announced the successful tapeout of their technology on an industry-standard nm process.
With the new cash, the company plans on ramping up its R&D as well as pushing forward the commercial readiness of its products. According to Eliyan, the company’s first silicon is expected in the first quarter of 2023.