The Data Center Spike: Micron Prepares by Rolling Out DDR5

By 2024, the US data center market is expected to reach revenues of over 69 billion USD. With increasingly more companies and users relying on data centers for operations and daily use, having reliable hardware and software is crucial to keep these services up and running.

 

Micron’s DDR5 features two 40- bit independent channels. Image used courtesy of Micron

 

One major way to accomplish this is to improve memory performance—something Micron recently announced with its sampling of their DDR5 Registered DIMMs (RDIMM). 

 

Performance Improvements of DDR5 

Micron’s DDR5 is the fifth-generation double data rate (DDR) SDRAM. (PDF) DDR5 is the successor of DDR4 and comes with significant improvements. 

 

Effective bandwidth of DDR4 vs. DDR5. Image used courtesy of (PDF) Micron

 

Looking at the performance of the DDR4 and DDR5 at an equivalent data rate of 3200 megatransfers per second (MT/s), DDR5 has a performance increase of 1.36 times effective bandwidth. At a higher data rate, 4800 MT/s, DDR5 performance increase becomes 1.87 times that of the DDR4.

This comes at a time when rapidly expanding datasets and compute-intensive applications have lead to the growth of processor core count “which will be bandwidth-starved by current DRAM technology.” 

Micron states that DDR is the most technologically advanced DRAM to date and will enable the next generation of server workloads by offering an 85% increase in memory performance.

 

New Features Enabling Data Rate Increases

There are many key additions and improvements that enable the DDR5’s bandwidth increase. These include:

•  A duty cycle adjuster (DCA) circuit to correct small duty cycles that occur in DQ and DQS signals received by the controller 
• DQS interval oscillator circuit that allows the controller to monitor changes in DQS clock delays due to changes in voltage and temperature
• Improved training modes that include a new READ preamble training mode, command and address training mode, chip select training mode, and a write leveling training mode 
• Write leveling allows the system to compensate for timing differences on a module between the CK path to each DRAM device and DW and DWS paths. 
• Read training patterns with dedicated mode registers 
• Internal reference voltages for the command and address pins, chip select pin, and DQ pins

 

Reliability, Availability, and Serviceability (RAS) 

Modern data centers require reliability, availability, and serviceability, which can be enabled by several features of DDR5. 

On-Die Error Correction Code (ECC) reduces the system error correction burden by performing correction during READ commands prior to outputting the data from the DDR5 device. DDR5 designs implement EDD with Hamming codes.

 

Theoretical DRAM bandwidth vs. core count trend. Image used courtesy of Micron

 

Additionally, DDR5 SDRAM ECC has an error check and scrub (ECS) function, which is a read of internal data and writing back corrected data if an error has occurred. ECS can be used as a manual or automatic function. 

Post-package repair (PPR) is a feature with a hard (HPPR) and soft (sPPR) mode. These two modes correspond to permanent repair and temporary repair, respectively. PPR also has the ability to track resource availability.

At boot-up, each DRAM device determines the availability of a PPR resource in each bank and then sets a group of mode registers to track information. 

Micron’s portfolio of DDR5 SDRAM products offers a plethora of features aimed to bring innovation and higher performance to data centers.