Technical Article

Introduction to DRAM (Dynamic Random-Access Memory)

August 01, 2019 by Stephen St. Michael

This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.

This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.

What Is DRAM?

Memory is fundamental in the operation of a computer. When combined with a CPU, the ability to run sets of instructions (programs) and store working data becomes possible. Random-access memory (RAM) is a well-known type of memory and is so-called because of its ability to access any location in memory with roughly the same time delay.

Dynamic random access memory, or DRAM, is a specific type of random access memory that allows for higher densities at a lower cost. The memory modules found in laptops and desktops use DRAM.



Other types of memory like SRAM, MRAM, and Flash may be discussed in a future article. In short, however, where DRAM stands for dynamic random-access memory, SRAM stands for static random-access memory. The largest differences are that DRAM utilizes capacitors (as we'll discuss later in this article) where SRAM does not, though there are also considerations such as different processing, different speeds, and different cost for developers.

How Does DRAM Work? 

Invented by Robert Dennard in 1966 at IBM, DRAM works much differently than other types of memory. The fundamental storage cell within DRAM is composed of two elements: a transistor and a capacitor.

When a bit needs to be put in memory, the transistor is used to charge or discharge the capacitor. A charged capacitor represents a logic high, or '1', while a discharged capacitor represents a logic low, or '0'. The charging/discharging is done via the wordline and bitline, shown in Figure 1. 

Figure 1. In DRAM a bit is stored as the presence or absence of charge on a capacitor


During a read or write, the wordline goes high and the transistor connects the capacitor to the bitline. Whatever value is on the bitline ('1' or '0') gets stored or retrieved from the capacitor. 

The charge stored on each capacitor is too small to be read directly and is instead measured by a circuit called a sense amplifier. The sense amplifier detects the minute differences in charge and outputs the corresponding logic level. The act of reading from the bitline forces the charge to flow out of the capacitor. Thus, in DRAM, reads are destructive. To get around this, an operation known as precharging is done to put the value read from the bitline back into the capacitor.

Equally problematic is the fact that the capacitors leak charge over time. Therefore, to maintain the data stored in memory the capacitors must be refreshed periodically. Refreshing works just like a read and ensures data is never lost. This is where DRAM gets the “Dynamic” moniker from—the charge on a DRAM cell is dynamically refreshed every so often. Contrast this with SRAM (Static RAM) which retains its state without needing to be refreshed.

How Is DRAM Organized?

DRAM can come in different forms depending on the application. Figure 2 shows a DIMM (dual inline memory module) that contains multiple onboard DRAM chips. 


Figure 2. 1 GB DIMM containing a number of DRAM chips


This DIMM contains 1 GB of memory, but notice the “2Rx8” printed on the sticker. The 2R means that this module is of rank 2, while the x8 (pronounced “by eight”) denotes the output width of the data coming from each DRAM chip. A rank is a separately addressable set of DRAMs. In this case, one rank is a set of four DRAM chips. Since there are eight total (front/back), we have 2 ranks.  

The rank of a DRAM module is the highest level of organization within a DIMM. Below that, each chip is organized into a number of banks and memory arrays containing rows and columns. Figure 3 shows a DRAM chip with four banks. 


Figure 3. DRAM chip with four banks


Each bank operates independently of the others. This means that reading, writing, and precharging can all be done on one bank without impacting the other.

Rank, Bank, Row, and Column

As mentioned earlier, the rank of a DRAM is a set of separately addressable DRAM chips. Each DRAM chip is further organized into a number of banks that contain a set of memory arrays. The number of memory arrays per bank is equal to the size of the output width. Therefore in a x4 DRAM chip, the internal banks would each have four memory arrays. Figure 4 shows an example of a single x4 bank.


Figure 4. A x4 bank composed of decoders, sense amplifiers, and memory arrays


The gray section is the memory array designed as a grid of rows and columns. A set of decoders are used to access the rows and columns, selecting a single intersection within the memory array. It is at this intersection that a small capacitor stores a charge representing the data being accessed.

Sense amplifiers perform precharge operations on capacitors and generate logic-level outputs for a number of data buffers that store the data until it can be retrieved by a memory controller or CPU.


In this article, we examined the basic principle of operation behind dynamic random access memory, or DRAM. DRAM is extremely common in personal computers and is a basic component that any computer needs to work properly. DRAM works by using the presence or absence of charge on a capacitor to store data.

Since a single DRAM cell is composed of only two components—a transistor and a capacitor—DRAM can be made in high densities, and it is inexpensive compared to other types of memory. We also looked at a DIMM containing multiple DRAM chips and how those DRAM chips are organized into arrays of memory cells.

The next DRAM article will discuss the commands used to control and exchange data with a DRAM chip. See you there!