Technical Article

Introduction to MOSFET Switching Losses

April 28, 2024 by Robert Keim

This article will help you optimize your switch-mode regulator and driver circuits by explaining important sources of MOSFET power dissipation.

MOSFET operation can be divided into two basic modes: linear and switching. In linear mode, the transistor’s gate-to-source voltage is sufficient to enable current flow through the channel, but the channel resistance is relatively high. The voltage across the channel and the current flowing through the channel are both significant, resulting in high power dissipation in the transistor.

In switching mode, the gate-to-source voltage is either low enough to prevent current flow or high enough to place the FET in a “fully enhanced” state in which channel resistance is greatly reduced. In this state, the transistor acts like a closed switch: even if large currents flow through the channel, power dissipation will be low or moderate.

As switch-mode operation approaches the ideal case, power dissipation becomes negligible. The switch is either fully inactive, with zero current and therefore zero loss, or fully active, with minimal resistance and therefore minimal loss. Because of its high efficiency, switching mode is used in many applications—digital CMOS circuits, power supplies, and Class D amplifiers all come to mind.

Real-life MOSFET switching, however, involves losses that designers will often need to consider when selecting parts and laying out circuit boards. In this article, we’ll discuss three types of unintended power dissipation:

  • Conduction loss.
  • Switching loss.
  • Gate-charge loss.


Conduction Loss

Conduction loss is the power dissipated when current flows through the non-zero resistance of a MOSFET’s channel. The drain-to-source resistance of a fully enhanced MOSFET is denoted by RDS(on).

Figure 1, which is taken from the datasheet for Onsemi’s NDS351AN MOSFET, shows how channel resistance decreases as gate-to-source voltage increases. The fully enhanced state corresponds to the low-slope portions of the curves.


Channel resistance vs. gate-to-source voltage for the NDS351AN MOSFET from Onsemi.

Figure 1. Channel resistance versus gate-to-source voltage for the NDS351AN MOSFET. Image used courtesy of Onsemi


The instantaneous conduction loss (PC) can be calculated using one of the standard formulas for electric power:


Equation 1.


where ID is the FET’s drain-to-source current.

We can also calculate a time-averaged conduction loss using RMS current instead of instantaneous current:


Equation 2.


Since we assume that the amount of current flowing through the MOSFET is governed by application requirements, the way to reduce conduction loss is to reduce RDS(on). This is accomplished first of all through careful part selection—some modern FETs, including silicon carbide and gallium nitride, offer extremely low RDS(on).

Beyond that, you should also ensure that operating conditions and surrounding circuitry help the FET to reach its lowest possible channel resistance. Even fractions of an ohm can be significant when large currents are required, such as in Figure 2’s buck converter.


Flow of current through an LTspice buck converter.

Figure 2. The load current in a buck converter must flow through the channel resistance of the switching element, which is usually a MOSFET. Image used courtesy of Robert Keim


Switching Loss

In the simplified model of switch-mode operation, a MOSFET is either fully on or fully off. However, a more realistic model must acknowledge that the transition between the two states isn’t instantaneous. Instead, the FET operates briefly in the high-power-dissipation linear mode every time it switches. This leads to a second type of loss, known as switching loss.

Calculating switching loss isn’t straightforward, since the transition between on and off states is a highly dynamic process during which the channel resistance exhibits continuous change. The formula in Equation 3 is suggested by ROHM Semiconductor in this application note.


Equation 3.


This equation indicates that switching loss (PSW) depends on all of the following:

  • The voltage used to drive switched current through the FET (VIN).
  • The FET’s drain current (ID).
  • The rise and fall time of the switching waveform (tR and tF).
  • The switching frequency (fSW).


Gate-Charge Loss

All MOSFETs have an insulating layer that prevents current flow through the gate terminal—it’s part of what distinguishes them from other types of field-effect transistors. Strictly speaking, however, this insulation blocks only steady-state current. As shown in Figure 3, a MOSFET’s insulating gate is a capacitive structure; transient current therefore flows in a gate-drive circuit until the gate capacitor is fully charged or discharged.


MOSFET diagram showing the capacitive gate structure and a drain-to-source current channel.

Figure 3. In this MOSFET diagram, an applied gate-to-source voltage has created a channel for drain-to-source current flow. Image used courtesy of Tony R. Kuphaldt


This constitutes yet another source of dissipative loss for switch-mode MOSFETs. Turning the FET on and off requires changes to the gate voltage, and power dissipation occurs when the resulting transient currents flow through parasitic resistances.

The formula for gate-charge loss (PGC) is given by Equation 4.


Equation 4.



QG is the total gate charge required by the FET

VGS is the gate-to-source voltage

fSW is the switching frequency.

Equation 4 leads us to an important observation. A MOSFET with higher gate-charge requirements will reduce efficiency, and thus designers are faced with a trade-off: larger gate area helps to reduce RDS(on) and therefore to reduce conduction loss, but larger gate area also increases QG and therefore increases gate-charge loss.


Wrapping Up

MOSFET-based switching circuits often achieve much higher efficiency than circuits that rely on linear modes of transistor operation. Nonetheless, switching losses do occur. The ability to estimate these losses can help you to optimize your design and avoid potentially serious thermal failures.