MOSFET NonIdealities in Analog IC Design
MOS transistors exhibit a wide variety of secondorder effects not covered by ideal models. To design analog integrated circuits that will work in the real world, we need to understand these nonidealities.
In the previous article, we introduced the basic MOSFET structure and operating regions. The models we discussed depicted an ideal MOSFET, and were fairly accurate for early MOS transistors due to their long channel sizes. However, subsequent research and the continued miniaturization of transistors have both revealed a slew of nonidealities in transistor behavior. This article will go over the basics of these nonidealities and how they affect transistor performance in analog integrated circuits.
Parasitic Capacitances
Due to the physical implementation of the MOSFET, the following parasitic capacitances are formed between terminal junctions:
 C_{GS}: gatetosource capacitance.
 C_{GD}: gatetodrain capacitance.
 C_{GB}: gatetobody capacitance.
 C_{SB}: sourcetobody capacitance.
 C_{DB}: draintobody capacitance.
When designing analog ICs that include MOSFETs, these capacitances play a large role in circuit bandwidth. Figure 1 illustrates their locations.
Figure 1. MOSFET structure with parasitic capacitances.
The capacitance values change with respect to the operating region, as we’ll discuss in the coming sections.
GatetoSource and GatetoDrain Capacitances
While this isn’t shown in Figure 1, the source and drain extend slightly under the gate during transistor fabrication. In the area where the gate overlaps either the source or the drain, a capacitor forms with the gate oxide (SiO_{2}) as the dielectric between them. The length of this overlap is called L_{diff}.
The value of the gatetosource (or drain) capacitor formed by the oxide capacitance (C_{ox}) can be calculated as:
$$C_{GS}~=~C'_{ox}~\times~W~\times~L_{diff}$$
Equation 1.
where:
C’_{ox} is equal to \(\frac{\epsilon_{ox}}{t_{ox}}\)
ε_{ox} is the dielectric constant for silicon dioxide
t_{ox} is the thickness of the gate oxide (the height shown in Figure 1).
This simple equation for gatetosource (or drain) capacitance is valid only when the source and drain are separated from each other, which is true when the transistor is in either cutoff or saturation (since the channel pinches off). In the linear region, the source and drain channels are effectively “shorted” by a resistive channel, so we only need to concern ourselves with the oxide capacitance between gate and channel.
Because the device is symmetric, in the linear region we can assume that the source and drain will each take half of the oxide capacitance value. The gatetosource and gatetodrain values can be calculated as:
$$C_{GS}~=~C_{GD}~=~\frac{1}{2}~\times~W~\times~L~\times~C'_{ox}$$
Equation 2.
GatetoBody Capacitance
The value of C_{GD} actually consists of the parallel combination of two separate capacitors:
 The oxide capacitor, located between the gate and the substrate.
 The depletion capacitor, which forms between the depletion layer (the area between the channel and substrate) and the substrate.
The oxide capacitance value can be calculated using the following equation:
$$C_{ox}~=~C'_{ox}~\times~W~\times~L$$
Equation 3.
and the depletion capacitance, using this one:
$$C_{dep}~=~CGBO~\times~W~\times~L$$
Equation 4.
where CGBO is a gatebulk overlap capacitance term dependent on the transistor’s physical characteristics.
The oxide and depletion capacitors are in parallel with one another—when both are present, they sum together. In the cutoff region, because there’s no channel between the gate and body, the value of C_{GB }is the sum of Equations 3 and 4. Once a channel is present, C_{ox} is disconnected from the body, as we discussed previously with the gate to source/drain capacitances. The value of C_{GD} is therefore equal to C_{dep}, and can be found using Equation 4.
SourcetoBody and DraintoBody Capacitances
Deriving the values of C_{SB} and C_{DB} involves a decent amount of device physics. These values are determined by the junction capacitance (C_{J}). The value of C_{J} is determined by the depletion area width, which in turn is based on the doping concentration within the MOSFET.
All we need to take away from this is that C_{SB} and C_{DB} will remain constant at the junction between the source or drain and the body, since the size of the terminals do not change between operating regions.
Summary of Capacitance Values
Table 1 summarizes the parasitic capacitance values of the MOSFET by operating region.
Table 1. Parasitic capacitance values.
Capacitance  Cutoff  Linear  Saturation 
C_{GS} and C_{GD} 
\(C'_{ox}~\times~W~\times~L_{diff}\)

\( \frac{1}{2}~\times~W~\times~L~\times~C'_{ox}\)  \( C'_{ox}~\times~W~\times~L_{diff}\) 
C_{GB} 
\(C_{ox}~+~C_{dep}\)

\(C_{dep} \)  \(C_{dep} \) 
C_{SB} and C_{DB} 
\( C_{J}\)

\( C_{J}\)  \( C_{J}\) 
The Body Effect
We previously discussed how the body and source terminals of the transistor are normally connected to the same potential, but didn’t go over why this is. To understand why, let’s take a deeper look at the physical transistor as the value of V_{GS} increases from 0 to greater than the threshold voltage (V_{th}).
As V_{GS} slowly increases from zero, positive holes within the silicon are pushed away from the gate, leaving behind negatively charged ions. This creates a depletion layer—a region in which no charge carriers exist. As V_{GS} continues to increase, the gate charge begins to slowly grow larger than that of the depletion layer, and thus a channel of electrons can form between the source and drain.
Let’s assume that the body voltage becomes more negative than the source (V_{SB} > 0). More holes are now attracted to the body terminal, causing a larger depletion region to form near the channel. This means an increase in the threshold voltage, since a larger gate voltage is now required to overcome the charge of the depletion region and form a channel. The opposite occurs when V_{SB} < 0: a smaller depletion region forms near the channel, and V_{th} decreases in response.
The body effect is shown in Figure 2.
Figure 2. I_{D} vs. V_{GS} with varying V_{SB} (light blue: V_{SB} = 0 V; green: V_{SB} = –0.5 V; red: V_{SB} = 0.5 V).
The threshold voltage with respect to the body effect can be calculated as:
$$V_{th}~=~V_{th0}~+~\gamma \sqrt{2 \Phi_{F}~+~V_{SB}}~~\sqrt{2 \Phi_{F}}$$
Equation 5.
where:
V_{th0} is the nominal threshold voltage
Φ_{F} is the Fermi potential of the silicon.
The body effect has a big impact on analog designs—it’s very popular to stack transistors on top of one another, which causes the body effect to change the threshold voltages in a nontrivial way.
Channel Length Modulation
In theory, a transistor in saturation should act as a perfect current source with infinite output resistance. In reality, V_{DS} still has an effect on the drain current when the channel pinches off, and so the transistor’s output resistance is large but finite. This is due to a phenomenon called channel length modulation, in which the channel length begins to gradually decrease as the drain voltage increases in the saturation region.
To accommodate channel length modulation, we adjust the drain current equation in saturation to:
$$I_{D}~=~\mu C_{ox} \frac{W}{L}( V_{GS}~~V_{th})^{2} ( 1~+~ \lambda V_{DS} )$$
Equation 6.
The channel length modulation coefficient, λ, is calculated by:
$$\frac{\Delta L}{L} V_{DS}~=~\lambda$$
Equation 7.
From this, we can calculate the output resistance (R_{OUT}) in saturation to be:
$$R_{OUT}~=~\frac{1}{ \mu \lambda C_{ox} \frac{W}{L} ( V_{GS}~~V_{th})^{2} }$$
Equation 8.
Subthreshold Conduction
Previously, we defined three transistor operating regions: cutoff, linear, and saturation. In reality, there’s a fourth: the subthreshold region, which has become very popular in ultralow power analog IC designs.
This region forms because the transistor doesn’t turn off exactly as V_{GS} becomes lower than V_{th}. Instead, diffusion currents make up a small channel between the source and drain. When V_{GS} < V_{th}, this diffusion current is nonnegligible and has an exponential dependence on V_{GS}. The IV curve of the resulting subthreshold region is calculated as:
$$I_{D}~=~I_{S}e^{(\frac{V_{GS}}{ \xi V_{T}})}$$
Equation 9.
where:
I_{S} is the specific current of the transistor, and is proportional to \(\frac{W}{L}\)
ξ is a nonideality factor (> 1 in silicon)
V_{T} is the thermal voltage, and equal to \(\frac{k\text{T}}{q}\).
Mobility Degradation and Velocity Saturation
The drift current within the transistor is determined by the internal electric field, and as transistors have been scaled down, their electric fields have increased rapidly. As it turns out, for shortchannel transistors there is a maximum velocity of minority carriers that can be achieved within the transistor. This is known as the saturation velocity.
This limits the current increase with respect to V_{GS} and V_{DS} for certain devices, as eventually their drive current tops out. Furthermore, as electric fields continue to increase, the mobility of these carriers degrades, causing a decrease in drive current at these very high voltages. This shortchannel effect is one of many aspects of modern transistor behavior that can’t be predicted by the squarelaw equations we looked at in the preceding article.
DrainInduced Barrier Lowering (DIBL)
When V_{DS} becomes large enough, the drain begins to attract negative charge to the surface under the gate, helping the gate to create a channel. The effective threshold voltage decreases as a result, creating a relationship in which V_{th} is inversely proportional to V_{DS}. This is known as draininduced barrier lowering, or DIBL for short.
PVT Variations
Variations in process, voltage, and temperature, together referred to as PVT, collectively make up the last nonideality we’ll discuss.
When transistors are fabricated, manufacturing process variation is inevitable. Process variation can change important transistor characteristics, resulting in different threshold voltages, carrier mobilities, and parasitic capacitances, among other effects. These process variations are often contained within four “corners”: fastfast, fastslow, slowfast, and slowslow. The corners describe the relative speed of the PMOS and NMOS transistors based on worstcase manufacturing statistics.
Beyond that, variation from one transistor to another is tested via a Monte Carlo analysis that uses models containing statistical data on fabricated transistor parameter variation. Analog designers must utilize both the Monte Carlo and corners methods, as mismatch can have devastating effects on circuit performance.
Finally, operating voltage and ambient temperature also affect transistor performance. These environmental conditions must be checked during the IC design process to ensure the final product operates to specifications.
All images used courtesy of Nicholas St. John