TTL Logic Gates

Explain why it is generally a very bad design practice to connect the outputs of different logic gates together, like this:

However, there are certain specific circumstances in which “paralleling” gate outputs is acceptable. For instance, it is okay to parallel two or more inverters, like this:

No damage will be done if open-collector gate outputs are paralleled, either (although the resulting logic function may be strange):

And finally, gates that have tri-state outputs may also have their outputs paralleled if certain precautions are taken:

What, specifically, causes gates to be damaged by “paralleling” their outputs? Generally speaking, what principle must be followed in order to “parallel” logic gate outputs without risk of damage? Explain how each of the three acceptable “paralleled” scenarios shown here meet this criterion.

Suggestion: the issue of multiple gates having to output logic voltage signals onto common conductors (“busses”) is called bus contention. Try looking for this term in your research to see what useful information you find on paralleled gates!

An important parameter of logic gate circuitry is noise margin. What exactly is “noise margin,” and how is it defined for logic gates?

Specifically, how much noise margin do digital circuits exclusively composed of TTL gates have?

Note: you will need to consult TTL gate datasheets to answer this question properly.

Predict how the operation of this logic gate circuit will be affected as a result of the following faults. Consider each fault independently (i.e. one at a time, no multiple faults):

Diode D₁ fails open:

Diode D₁ fails shorted:

Diode D₂ fails open:

Resistor R₁ fails open:

Resistor R₂ fails open:

Resistor R₄ fails open:

For each of these conditions, explain why the resulting effects will occur.