Simple AES3 / SPDIF Compatible Receiver
Details
Category: Communication Controller
Created: April 19, 2009
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Features
- AES3 / SPDIF compatible receiver
- locks to any sample rate from 20kHz to 100kHz with 50MHz master clock and reg_width = 5
- locks to any sample rate from 20kHz to 200kHz with 100MHz master clock and reg_width = 6
- very compact (only 39 macrocells with reg_width = 5)
News
- 2009/08/31 - Fixed previous fix - removed redundant bbbr_shift_reg_proc.
- 2009/08/30 - Fixed bug preventing the receiver to lock on input signal in case that shortest pulse length was longer then master clock/2^reg_width. Also simple testbench has been uploaded to SVN.
- Design is finally done and FPGA proven. Fundamental changes (instead of measuring shortest pulse length, feedback is used for locking on the input signal) were made in last revision, so please update your copies.
Overview
AES3 / SPDIF receiver is simple, minimalistic but powerful core which decodes biphase mark coded AES3 compatible signal and retransmitts it in I2S-like format. Audio words are coded in 2's complement format, however, in contrast to I2S, they are LSb and not MSb aligned and all auxiliary bits of AES3 are left unchanged and transmitted together with audio word. There is even some mess in first four bits of each word as result of preamble detection. Nevertheless, this core can be implemented on XC9572XL-5 with only 43 macrocells utilization and fmax around 100MHz while capable of receiving AES3 at fs = 96kHz with clk at 50MHz.
