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Details
Category: Communication Controller
Created: Dec 05, 2007
Updated: Nov 19, 2019
Language: VHDL
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
Ever needed a pulse at a given frequency ( period ).
Well that is what BaudGen gives you.
By the use of parameters, you specify the frequency of the clock you wish to divide, the period ( baud rate ) you wish out, and optionally, how fast you want an over sample output.
BaudGen works out the required count values, and outputs one clock wide pulses at the required rate.
