HDB3/HDB2/B3ZS Encoder Decoder

HDB3/HDB2/B3ZS Encoder Decoder


Category: Communication Controller

Created: April 27, 2003

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: BSD


This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.

Note: HDB2 and B3ZS are different names for the same encoding.

HDB3 is typically used to encode data at 2.048 (E1), 8.448 (E2) and 34.368Mb/s (E3)
B3ZS is typically used to encode data at 44.736Mb/s (T3)


- HDB3 / HDB2 selected by a generic.
- Code Error output on decoder.
- P and N outputs (on encoder) or inputs (on decoder) may be active high or active low, selected by a generic.
- P and N outputs on encoder may be controlled to be “full width” (NRZ) or “half width” (RZ) to suit the external LIU.


- Alpha tests look good.
- Code and documentation available in the HDBN project in CVSWeb