I2C Bus Traffic Logger

I2C Bus Traffic Logger


Category: Communication Controller

Created: July 25, 2003

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a



- Captures I2C 2 wire serial bus activities into an external RAM
- Applicable to Atmel 2 wire serial bus format:
This includes (1) Random byte write
(2) Page write
(3) Random byte read
(4) Multiple start
- End of a transition after the stop bit is followed by an 8 bit count for simple time stamp.
- Code witten for 32K byte capacity, can be modified to higher capacity.
- Requires an external 2MHz to 5MHz clock.

I2C Bus Traffic Logger


Two wire serial I2C bus is designated as the communication standard in physical layer (PHY) transponders for link status monitoring purposes. The host routinely queries the transponder for informations such as errors, temperatures and configuration settings. The host also exercise controls to the transponder by writing into registers.

A complete specification of I2C bus can be found in Philips semiconductor web site semiconductors.philips.com/buses/i2c/index.html) . The implementation of the I2C bus protocol varies with vendors. This traffic logger dsign is compliant to the ATMEL serial EEPROMS data 2 wire serial bus format.

The use of a bus traffic log is primarily for monitoring and diagnostic link failures. In order to be useful, the traffic logger has to be able to capture large volumes of time stamped transactions for analysis.


- Project started