IICMB Core - I2C Multiple Bus Controller
Category: Communication Controller
Created: April 29, 2016
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
The IICMB core provides low-speed, two-wire, bidirectional serial bus interfaces compliant to industry standard I2C protocol.
The key feature of the core is its ability to control several connected I2C buses effectively reducing complexity of the system.
- Compatible with Philips' I2C standard
- Works with up to 16 distinct I2C buses
- Statically configurable system bus clock frequency
- Statically configurable desired clock frequencies of I2C buses
- Multi-master clock synchronization
- Multi-master arbitration
- Clock stretching
- Digital filtering of SCL and SDA inputs
- Standard (up to 100 kHz) and Fast (up to 400 kHz) mode operation
- Example connection as 8-bit slave on Wishbone bus
- Example connection as 32-bit slave on Avalon-MM bus
- Sequencer-based example, working without any system bus
Currently supported master mode only.
The slave mode is under development. Please, submit desired slave features.