OPB SPI Clock Independent Core
Details
Category: Communication Controller
Created: November 19, 2007
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request.
Features
- OPB-Clock and SPI-Clock are complete independent
- SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure.
- variable transfer length 2..32
- Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width)
Status
- simulation tests done
- Hardware tests on a Virtex-4 ML401 Board (LX25) done
- CRC-Code Real World Test in progress
