Facebook
Google
GitHub
Linkedin16550D UART in SystemVerilog IEEE 1800-2005
Details
Category: Communication Controller
Created: Mar 30, 2010
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
RS232 Protocol 16550D uart (mostly supported)
- language : systemVerilog IEEE 1800-2005 (Quaruts2-9.1sp1 Support)
- scale : fpga cyclone3 800cell, >50Mhz
- bus : wishbone
-
TODO:
Lin's automotive standards
-> subset of transport layer circuit
