Synchronous UART FIFO CPU Interface & SV Self-Checking Testbench

This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interface and a SystemVerilog transaction based self-checking testbench. The VHDL RTL is written in a "single process" style to improve code readability and lets the synthesis tool infer the flops and gates.

The cpu interface is simple (address, data in, data out, read enable, write enable).
Transmit and receive FIFO size is configurable with a generic.
Baud rate is register programmable.
Currently only support no parity bit, 8 data bits and 1 stop bit (N81).