Standalone SPISlave on Full Icarus Verilog Test Bench

Standalone SPISlave on Full Icarus Verilog Test Bench


Category: Communication Controller

Created: December 07, 2009

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


spislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spislave devices. The core provides a means to write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available.
Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer.Download and install Icarus Verilog. -
Download and install GTKWave.

- Download the project files. - For executing the testbench just run the Makefile on the bench folder.
In GTKWave, use "Search >> Signal Search Tree" to view more waves.


- Standalone. No microprocessor required. For master side we need an microntroller
- Create your own custom spislave peripheral.
- Easily configurable for different input clock frequencies.
- Full Icarus Verilog test bench.
- This is to be tested with Our Zkit-51( 8 bit microcon board),a lcd(16x2) and Xilinx Spartan 3A FPGA board


- Tested in Zkit - 51 (8 bit microcontroller board) with Xilinx Spartan 3A FPGA board.
- Tested in simulation.
- Tested waveform in GTK wave.