Non-blocking TDM Digital Switch Core on Xilinx Spartan II
Details
Category: Communication Controller
Created: May 03, 2003
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
The TDM_Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s. Some of the main features are: Processor Mode and input offset delay.
Features
- 256 x 256 channel non-blocking switching at 2.048 Mb/s
- Accept 8 serial data streams of 2.048 Mb/s
- Per-stream frame delay offset programming
- Connection memory block programming
- Microprocessor Interface
Status
This IP core is synthesized for Xilinx SPARTAN-II series FPGA’s, fit at xc2s50-6tq144 device and the post place & route simulation model simulate with Cadence NC-Sim simulator.
