UART to SPI Interface Core

UART to SPI Interface Core

Details

Category: Communication Controller

Created: January 15, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

The UART to SPI IP Core include a simple command parser that can be used to access an internal bus of SPI via a UART interface. This IP can be used understand the SPI transaction protocol. The internal bus is designed with address bus of 16 bits and data bus of 8 bits. The core implements a very basic UART transmit & receive blocks which share a common baud rate generator and a command parser. The parser supports text mode of command parsing. Text mode commands are designed to be used with hyper terminal software and enable easy access to the internal bus.

Block Diagram

UART2SPI Block Diagram