USB 2.0 Wishbone SoC Compliant Core

USB 2.0 Wishbone SoC Compliant Core


Category: Communication Controller

Created: September 25, 2001

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: Yes

WishBone version: n/a

License: n/a


This is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core. A industry standard PHY interface for USB has been developed. This interface is called USB Transceiver Macrocell Interface or UTMI for short. The host interface of the USB core will be WISHBONE SoC compliant. More information about the USB standard and a full specification can be found at More information about the WISHBONE SoC and a full specification can be found here. The UTMI specification (and various other useful USB papers) can be downloaded from here. For further information, questions and general discussions related to the USB core, please visit the USB Mailing list.


- 8/2/2001 New Directory Structure ! We have agreed on a common directory structure at OpenCores. - Second release is checked in ! [March 31, 2001] - The Core is now configurable - Moved buffer memory (SSRAM) outside the core - Many small fixes and additions (see usb_doc for more details) - This is still a development version, see the doc/STATUS file for the actual status - Please do not make any modifications on the sources as I'm still actively working on the core - Please submit bugs and comments to the bugtracker - PLEASE HELP: I'm still looking for people to help me verify the core

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