USB 1.1 PHY - A Verilog to VHDL Transalation

USB 1.1 PHY - A Verilog to VHDL Transalation


Category: Communication Controller

Created: February 10, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a Verilog to VHDL translation of Rudolf Usselmanns USB 1.1 PHY.
Since the original design operates with a 48 MHz clock and I required a 60 MHz version I added also a modified version with a 60 MHz clock section - the changes are only in file usb_rx_phy_60MHz.vhdl (the unmodified version usb_rx_phy.vhdl is also provided).
The design has been simulated using the USB 1.1 Simulation model.

An update to the usb_tx_phy.vhdl source corrects the recently reported bit-stuffing issue (USB spec:"If required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (EOP) signal.").
This issue caused very rare (but hard to find) problems.
This correction applies only the VHDL code (the original verilog code is not in this focus).