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LinkedinGeneric FIR Filter in RobustVerilog Parser
Details
Category: DSP Core
Created: Mar 23, 2011
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input. Builds Verilog FIR filter according to input parameters: multiplier number, filter order, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools
