Generic FIR Filter in RobustVerilog Parser

Generic FIR Filter in RobustVerilog Parser


Category: DSP Core

Created: March 23, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input. Builds Verilog FIR filter according to input parameters: multiplier number, filter order, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools