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Details
Category: Memory Core
Created: Apr 24, 2009
Updated: Nov 19, 2019
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
This is a wishbone B3 compliant RAM memory. The memory array is defined as a 32 bit memory. This gives two valuable benefits. First. memory array can be mapped into one block RAM with no need for byte select during synthesis. Second, memory content can be initialized with CPU instructions with no need to split content into byte chunks.
