Diogenes: Student RISC System

Diogenes: Student RISC System


Category: Processor

Created: February 01, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: n/a


This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture. Please note that it was developed on a Sparten-3E Starter Kit and memory in VHDL code is embedded via XILINX specific routines.


- Assembler
- Simulator
- Simple I/O (Leds, Buttons, UART, Hitachi LCD)
- VGA Controller


- presented in class as working