Edge Processor Microarchitecture Implementation for MIPS1 ISA
Details
Category: Processor
Created: March 01, 2014
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Edge is a microarchitecture implementation for mips1 ISA.
It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz frequency.
Supporting timer and other interrupt types and exceptions is implemented through co-processor0.
Edge has been tested and verified on Atlys that has a Spartan-6 XC6SLX45 FPGA.
For the Atlys board, UART driver is provided to communicate with PC at 115200 baud rate.
Youtube link for simple C programs running [1]
https://www.youtube.com/watch?v=Hxwq2KWzycU
