Mips-FaultTolerant 32-bit 5 Stages Core Processor
Created: January 22, 2013
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
A fault tolerant for processor
The mips – fault tolerant is mips 32 bits processor with error detection ( Fault Tolerant ). The processor implementation was designed by Lazaridis Dimitris.
The core is in 5 stages:
- Instruction extraction
- Instruction decoding
- Memory access
- Update registers
It supports almost all instructions of mips technology, R type, I type, Branch, Jump and multiply packet instructions.
The multiply result is stored until is needed regardless if others instructions follows.
There is an error detection circuits for fault tolerant. It is implementing in hardware 100% which provides error detection at reset start-up.
There is a separate memory for instructions and another for data read – write which can be changed.
At each stage one clock cycle is used. Both memories function in descending pulse and the remaining pulse is used for developing the necessary functions (e.g. pipeline), which makes the core faster and more flexible.
All I types instructions are part decoded in first stage and all R types also part decoded in Alu control reducing the complexity in main Control unit (FSM).
All instructions are tested for correct execution. A test benchs from separate circuit implementation is also included (to verify the program which exists in Instruction memory).
The mips - fault tolerant was integrated in an FPGA from Xilinx version 13.1 in Spartan 3 xc3s400-5tq144 target device but can be fit in another similar target device.
The processor is implemented all in VHDL.
With continuous scaling in CMOS technology the number of transistors grows more and more in a single chip. Chip multiprocessors (CMPs) are an efficient way for using this very large number of transistors integrated in a chip. Several researches show that high density integration makes modern processors prone to the risk of transient or permanent fault. However, the increase of temperature and decrease of the voltage in the chip lead to a higher susceptibility to faults. As the feature size shrinks the probability of a single transistor to become faulty, it increases due to the low threshold voltages.
It is projected that the rate at which the transient errors occur will grow exponentially and will soon represent one of the most significant issues in the design of future generation high-performance microprocessors.
This work proposes a fault tolerant architecture that tolerates the high fault rates that are expected in future technologies. In this work the multiplication block circuit is tested.
In this method a multiplication is executed and the result is stored following by a comparison. It is start with initial value of 00001111…. which this value executes a multiplication in multiplication circuit and the result is stored. It needs 64 machine cycles to complete this error detection. After the initial multiplication the numbers which are executed are subjected a shift one digit, following by a multiplication again and the result are stored in previous result. This is continuous for 64 machine cycle, where the final result is stored, including the previous results. In final stage of error detection the calculated result is compared with a correct stored result and if any error exists in multiplication array circuit this can be found. In this method the fault coverage is approximately 75% and 64 machine cycles are demanded. The error detection begins at start up before any execution. It has a high fault coverage and nearly fast execution due to hardware implementation, which will be more popular method for errors detection in future for the time saving (there is not time penalty), reliability, low cost and high presentence to fault coverage, low power consumption.
A slide different circuit implementation but much more powerful:
The multiplier circuit device made with and/h/f/adders.
C\AB 00 01 11 10
0 0 1 0 1
1 1 1c 0 1c
I treat both exits as one because the point is to detect errors, from the karnaugh map we have:
A’B + AB’ + CB’ If combine the first two we have CB’.
There is the term +AB (from 111, 110) but I subtract it temporally to simplify the procedure.
To implement it we need to include only one 0 in test vectors.
If we will check a 4X4 bits multiplier with a shift in each clock as:
1110, 1101, 1011, 0111 in y axes and the same in x axes, we will cover the 90% error detection in 8 machines cycles. I left one stage of variables out, for isolate detection to simplify the procedure, which is the value all -> 1s, which needs one machines cycle and cover the remaining 10% of error detection. The total procedure needs 10 machines cycles with an addition all -> 0s. The total coverage is 98-99%. In multiplier 32X32 bits it needs 66 machines cycles for total coverage. This method is fast enough and support total error detection with hardware implementation.
Another alternate method: This method is hardware implemented 100% also and it is very simple. In first machine cycle a 0000… is executed in multiplication circuit and the result is compared with 0, if a 1 stack exists can be found here. (This covers the 50% error detection)
In second cycle a number 1111111111111111111111111111111 is multiplied with the 10101010101010101010101010101010 and comparison is done with a correct stored value at the end of this cycle. The third and final stage a multiplication is done with reversed numbers to cover as much as possible of the multiplication array circuit and if any error detection exist is also found here. (In a sample multiplier 4X4 bits error detection coverage is about 2%) This method has smaller fault coverage about 54% but it is very fast, it is only need 3 machines cycles to complete the fault tolerance.
Most error detect methods for fault tolerance check the mips or a circuit at start up or at once or periodically to find any errors for fault coverage, but what if an error occurs during the tests? A fault data will process as correct. To work around with this, a non stop searching method is presented to test the mips continuously, it can be implement and find any error as it appears in born, further more if the fpga has enough space to relocate the damaged place it can be done in another undamaged.
To implement this error detect method, we can inject in fsm and detect the errors for fault tolerance. Knowing the next stage (instruction) through fsm, it is easy to start the test for “multiply” block circuits, which error detection circuit could test the multiply circuits as long as the next instruction it is not concern this circuits, if a multiply instruction is coming up we can stop the process and continue when it is free again, thus we can find if an error occurs in this part of cpu and cover the fault tolerance. The same process it is possible to test and other critical part of mips or central unit and find if an error exist. The advantage in this method is that the error detect circuit works continuously. This method does not require double cores, but only some additional parts (low cost) and which can work in conjunction with fsm without consume the microprocessor’s working time but it can work simultaneously.