Navré AVR Clone (8-bit RISC)

Navré AVR Clone (8-bit RISC) Click to expand image


Category: Processor

Created: August 05, 2010

Updated: November 19, 2019

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: GPL


Navré is part of the Milkymist System-on-Chip, the most advanced open source SoC for interactive multimedia applications.

  • Atmel AVR compatible
  • All Classic Core instructions implemented, except conditional branches on I/O registers
  • No interrupt support
  • Interrupt related instructions behave as if the I (interrupt enable) bit is hardwired to 0
  • Verilog-2001
  • Used to control the SoftUSB OHCI USB host
  • Fully synchronous
  • 2-stage pipeline
  • Almost cycle accurate with the original AVR. Most instructions execute in 1 cycle.
  • Synthesis results (ISE 12.2 default, post performance evaluation P&R, XC6SLX45-2): 1K LUTs, 11.7ns (85MHz) clock period

Testing wanted!

Even though simple C programs can be run, the Navré softcore still contains several bugs and testers are most welcome.

The idea is to use Verilog simulations to run and verify every instruction just like the simulavr test suite (which can be used for inspiration). Simple and incomplete test benches can be found with the SoftUSB core.

If you are interested in carrying out this work because you need an AVR compatible softcore in your design or just as a contribution to the Milkymist project, please contact the Milkymist-devel mailing list or drop by the #milkymist channel on the FreeNode IRC network.

I will happily fix any bug you may find!