OpenRISC 2000 Processor Architecture

OpenRISC 2000 Processor Architecture


Category: Processor

Created: July 12, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Planning

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


Status of the OpenRISC 2000

The development of the OpenRISC moved to
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).