OpenRISC 2000 Processor Architecture
Details
Category: Processor
Created: July 12, 2010
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Planning
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Status of the OpenRISC 2000
WARNING!
The development of the OpenRISC moved to OpenRISC.io
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).
