QRISC32 Wishbone Compatible RISC Core

QRISC32 Wishbone Compatible RISC Core


Category: Processor

Created: November 16, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

Additional info: Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


Project Qrisc32 is academic research and implementation of 4 stages risc cpu. Testbench runs 3 different sorting algorithms on qrisc32 and shows cycles for each turn. For observing instruction set, please refer to "risc_report.pdf" file. For running simulation you can use Modelsim with run_sim.tcl file.
Qrisc32 is implemented by using SystemVerilog.