R2000 Soc
Details
Category: Processor
Created: January 12, 2008
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
n/a
Category: Processor
Created: January 12, 2008
Updated: January 27, 2020
Language: Verilog
Development Status: Alpha
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
In Partnership with Würth Elektronik eiSos GmbH & Co. KG
by Aaron Carman
