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RISCOmpatible - an Implementation for RISCO Architecture

RISCOmpatible - an Implementation for RISCO Architecture

Details

Category: Processor

Created: Aug 01, 2014

Updated: Jan 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: LGPL

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Description

This project is an implementation of a processor compatible with the instruction set of the RISCO architecture.
A description of the original RISCO ISA is available on http://hdl.handle.net/1018321530.
An assembler and a compiler are available on https://code.google.com/p/risco-llvm.

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