SCARTS Processor for Embedded Systems with Real-time Requirements
Details
Category: Processor
Created: September 12, 2011
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The SCARTS processor is small and flexible processor, which has been specifically designed for embedded systems with real-time requirements. The deterministic architecture (all instructions execute in a single cycle) and the support of conditional instructions significantly simplify the task of WCET analysis. For SW development there is a toolchain based on the GNU Binutils/GCC/GDB. Furthermore there is a port of the Red Hat Newlib, a C standard library for embedded systems.
Features
- RISC processor
- 122 instructions, all single cycle
- Most instructions conditional
- 4 stage pipeline
- 16-bit architecture
- Data path extensible to 32 bit
- Almost the same ISA
- Higher performance, large address space
- Area increase about 70%
- 16 registers (14 general purpose registers)
- 16 interrupts, 16 traps
- 4 framepointer
- Extensible with hardware accelerators