Configurable PDP-8 Processor Core and System
Created: July 08, 2012
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
The PDP-8 was one of the earliest minicomputers and was in use from the mid 1960s into the 1980s.
Because the PDP-8 was relatively inexpensive and was available in various forms for many years, the PDP-8 is remembered fondly by many programmers and engineers
This project implements a complete PDP-8 system. The system includes the many of the basic PDP-8 peripherals including:
- Configurable PDP-8 CPU
- MS8C 32K-word memory
- KC8E Front Panel
- KE8 Extended Arithmetic Element
- KM8E Extended Memory
- KM8E Time Sharing
- DK8EA/DK8EC/DK8EP Real Time Clock
- KL8E Asynchronous Serial Interface (x2)
- LS8E Printer Interface
- PR8E Paper Tape Reader
- KL8E Disk Controller with 4 RK05 Disks Attached
The system passes all relevant diagnostics (MAINDECs) with the exception of the RK8E Disk Controller. The system boots OS/8 and runs all applications.
The design has been implemented and tested on a Digilent NEXYS2 Evaluation Board using the Xilinx ISE Webpack Version 13.3 toolset.
Note: The 1200K Gate version of the NEXYS2 board is required because all 32K words of RAM are implemented in FPGA block RAM.
The design has been implemented and tested on a Altera DE2-115 Evaluation Board using the Quartus II 11.1 Build 173 Full Version toolset.
The design has been implemented and tested on a ORSoC ordb2a-ep4ce22 Board using the Quartus II 11.1 Build 173 Full Version toolset.
The design is currently being implemented on a Altera DE0-Nano Development and Education board using the Quartus II 12.0 Web Edition tool set.
The DE0-Nano is expected to be the least expensive platform for this device and is available at a cost of $86.25 from (among other places) Digikey.