RISC Core I - 4 Stage 16-Bit RISC Processor System
Details
Category: Processor
Created: December 29, 2001
Updated: January 27, 2020
Other project properties
Development Status: Planning
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based.
Additionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port.
This core wasn't designed for commercial but for educational use. RAM, ROM and the ports are designed with the schematic editor from Xilinx ISE. RAM and ROM are dual ported for an additional access over a pci bridge. The CPU is programmed in VHDL.
Remark
The papers are written in german.