Yellow Star - 32 bit R2000/R3000 Processor Implementation

Yellow Star - 32 bit R2000/R3000 Processor Implementation


Category: Processor

Created: December 12, 2001

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a


It is capable of executing 32bit instructions based on the MIPS R3000 microprocessor instruction set and has been tested running large blocks of compiled C code.
Fully functional and compatible interrupt system. Can handle all exceptions cleanly and correctly.
Two 2Kbyte (Data and Instruction) direct mapped caches with coherency.
Memory management unit with 64 Entry TLB fully compatible to original design.
Designed in Powerview package but can be distributed in hierarchical schematic EDIF
Warning: The manual stated instructions SWL, SWR, LWL and LWR which are not implemented. And there are known bugs in the code.
For more information go to
The processor was created using schematics and there is NO RTL VHDL or Verilog.


- 32 entry 32bit Register bank created out of Ram blocks to save space
- 5 Stage pipeline
- Two 2Kb caches
- 64 Entry CAM TLB
- Exact exception handling
- One coprocessor


- Tested running all instructions that are implemented.
- Tested and running correctly at 50MHz
- Memory menagement and caching buggy
- Looking for good schematic entry people to take control of the project
- Looking for people to convert the project files to other platforms


Free for commercial and non-commercial use as long as the author and warning notices are maintained.

This software is provided by Charlie Brej "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.

MIPS(R) and R3000(R) are registered trademarks of MIPS Technologies, Inc. in the United States and other countries. OpenCores and Charles Brej are not affiliated in any way with MIPS Technologies, Inc.